nv50.c 6.1 KB
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/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
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#include "nv50.h"
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#include <core/gpuobj.h>
#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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struct nvkm_vm *
nv50_bar_kmap(struct nvkm_bar *base)
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{
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	return nv50_bar(base)->bar2_vm;
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}

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int
nv50_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
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{
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	struct nv50_bar *bar = nv50_bar(base);
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	return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma);
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}

static void
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nv50_bar_flush(struct nvkm_bar *base)
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{
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	struct nv50_bar *bar = nv50_bar(base);
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	struct nvkm_device *device = bar->base.subdev.device;
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	unsigned long flags;
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	spin_lock_irqsave(&bar->base.lock, flags);
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	nvkm_wr32(device, 0x00330c, 0x00000001);
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	nvkm_msec(device, 2000,
		if (!(nvkm_rd32(device, 0x00330c) & 0x00000002))
			break;
	);
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	spin_unlock_irqrestore(&bar->base.lock, flags);
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}

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void
nv50_bar_bar1_wait(struct nvkm_bar *base)
{
	nvkm_bar_flush(base);
}

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void
nv50_bar_bar1_fini(struct nvkm_bar *bar)
{
	nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000);
}

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void
nv50_bar_bar1_init(struct nvkm_bar *base)
{
	struct nvkm_device *device = base->subdev.device;
	struct nv50_bar *bar = nv50_bar(base);
	nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
}

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void
nv50_bar_init(struct nvkm_bar *base)
{
	struct nv50_bar *bar = nv50_bar(base);
	struct nvkm_device *device = bar->base.subdev.device;
	int i;

	nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
	nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
	nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);
	for (i = 0; i < 8; i++)
		nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);
}

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int
nv50_bar_oneinit(struct nvkm_bar *base)
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{
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	struct nv50_bar *bar = nv50_bar(base);
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	struct nvkm_device *device = bar->base.subdev.device;
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	static struct lock_class_key bar1_lock;
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	static struct lock_class_key bar2_lock;
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	struct nvkm_vm *vm;
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	u64 start, limit;
	int ret;

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	ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
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	if (ret)
		return ret;

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	ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,
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			      &bar->pad);
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	if (ret)
		return ret;

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	ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd);
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	if (ret)
		return ret;

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	/* BAR2 */
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	start = 0x0100000000ULL;
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	limit = start + device->func->resource_size(device, 3);
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	ret = nvkm_vm_new(device, start, limit - start, start, &bar2_lock, &vm);
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	if (ret)
		return ret;

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	atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
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	ret = nvkm_vm_boot(vm, limit-- - start);
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	if (ret)
		return ret;

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	ret = nvkm_vm_ref(vm, &bar->bar2_vm, bar->pgd);
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	nvkm_vm_ref(NULL, &vm, NULL);
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	if (ret)
		return ret;

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	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2);
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	if (ret)
		return ret;

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	nvkm_kmap(bar->bar2);
	nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
	nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
	nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
	nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
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				   upper_32_bits(start));
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	nvkm_wo32(bar->bar2, 0x10, 0x00000000);
	nvkm_wo32(bar->bar2, 0x14, 0x00000000);
	nvkm_done(bar->bar2);
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	/* BAR1 */
	start = 0x0000000000ULL;
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	limit = start + device->func->resource_size(device, 1);
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	ret = nvkm_vm_new(device, start, limit-- - start, start, &bar1_lock, &vm);
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	if (ret)
		return ret;

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	atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
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	ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);
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	nvkm_vm_ref(NULL, &vm, NULL);
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	if (ret)
		return ret;

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	ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1);
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	if (ret)
		return ret;

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	nvkm_kmap(bar->bar1);
	nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
	nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
	nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
	nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 |
				   upper_32_bits(start));
	nvkm_wo32(bar->bar1, 0x10, 0x00000000);
	nvkm_wo32(bar->bar1, 0x14, 0x00000000);
	nvkm_done(bar->bar1);
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	return 0;
}

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void *
nv50_bar_dtor(struct nvkm_bar *base)
{
	struct nv50_bar *bar = nv50_bar(base);
	nvkm_gpuobj_del(&bar->bar1);
	nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
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	nvkm_gpuobj_del(&bar->bar2);
	if (bar->bar2_vm) {
		nvkm_memory_del(&bar->bar2_vm->pgt[0].mem[0]);
		nvkm_vm_ref(NULL, &bar->bar2_vm, bar->pgd);
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	}
	nvkm_gpuobj_del(&bar->pgd);
	nvkm_gpuobj_del(&bar->pad);
	nvkm_gpuobj_del(&bar->mem);
	return bar;
}

int
nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
	      int index, u32 pgd_addr, struct nvkm_bar **pbar)
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{
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	struct nv50_bar *bar;
	if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
		return -ENOMEM;
	nvkm_bar_ctor(func, device, index, &bar->base);
	bar->pgd_addr = pgd_addr;
	*pbar = &bar->base;
	return 0;
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}

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static const struct nvkm_bar_func
nv50_bar_func = {
	.dtor = nv50_bar_dtor,
	.oneinit = nv50_bar_oneinit,
	.init = nv50_bar_init,
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	.bar1.init = nv50_bar_bar1_init,
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	.bar1.fini = nv50_bar_bar1_fini,
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	.bar1.wait = nv50_bar_bar1_wait,
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	.kmap = nv50_bar_kmap,
	.umap = nv50_bar_umap,
	.flush = nv50_bar_flush,
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};
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int
nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
{
	return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar);
}