sun7i-a20.dtsi 33.7 KB
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/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
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 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
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 *
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 *  a) This file is free software; you can redistribute it and/or
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 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
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 *     This file is distributed in the hope that it will be useful,
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 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
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 */

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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/ {
	interrupt-parent = <&gic>;

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	aliases {
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		ethernet0 = &gmac;
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	};

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	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		framebuffer@0 {
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			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
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			allwinner,pipeline = "de_be0-lcd0-hdmi";
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			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
				 <&ccu CLK_HDMI>;
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			status = "disabled";
		};
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		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
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			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
				 <&ccu CLK_DRAM_DE_BE0>;
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			status = "disabled";
		};

		framebuffer@2 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
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			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
				 <&ccu CLK_AHB_DE_BE0>,
				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
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			status = "disabled";
		};
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	};

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	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

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		cpu0: cpu@0 {
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			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
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			clocks = <&ccu CLK_CPU>;
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			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
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				/* kHz	  uV */
				960000	1400000
				912000	1400000
				864000	1300000
				720000	1200000
				528000	1100000
				312000	1000000
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				144000	1000000
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				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
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			cooling-max-level = <6>;
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		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

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	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

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	memory {
		reg = <0x40000000 0x80000000>;
	};

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	timer {
		compatible = "arm,armv7-timer";
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		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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	};

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	pmu {
		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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	};

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	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		osc24M: clk@1c20050 {
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			#clock-cells = <0>;
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			compatible = "fixed-clock";
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			clock-frequency = <24000000>;
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			clock-output-names = "osc24M";
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		};

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		osc32k: clk@0 {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
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			clock-output-names = "osc32k";
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		};
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		/*
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		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
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		 */
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		mii_phy_tx_clk: clk@1 {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

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		gmac_int_tx_clk: clk@2 {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

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		gmac_tx_clk: clk@1c20164 {
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			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};
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	};
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	de: display-engine {
		compatible = "allwinner,sun7i-a20-display-engine";
		allwinner,pipelines = <&fe0>, <&fe1>;
		status = "disabled";
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	};

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	soc@1c00000 {
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		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		sram-controller@1c00000 {
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			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

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			sram_a: sram@0 {
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				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
					compatible = "allwinner,sun4i-a10-sram-a3-a4";
					reg = <0x8000 0x4000>;
					status = "disabled";
				};
			};

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			sram_d: sram@10000 {
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				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

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				otg_sram: sram-section@0 {
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					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

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		nmi_intc: interrupt-controller@1c00030 {
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			compatible = "allwinner,sun7i-a20-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01c00030 0x0c>;
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			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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		};

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		dma: dma-controller@1c02000 {
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			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
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			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_DMA>;
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			#dma-cells = <2>;
		};

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		nfc: nand@1c03000 {
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			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
			dma-names = "rxtx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		spi0: spi@1c05000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
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			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <4>;
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		};

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		spi1: spi@1c06000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
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			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <1>;
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		};

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		emac: ethernet@1c0b000 {
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			compatible = "allwinner,sun4i-a10-emac";
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			reg = <0x01c0b000 0x1000>;
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			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_EMAC>;
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			allwinner,sram = <&emac_sram 1>;
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			status = "disabled";
		};

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		mdio: mdio@1c0b080 {
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			compatible = "allwinner,sun4i-a10-mdio";
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			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		tcon0: lcd-controller@1c0c000 {
			compatible = "allwinner,sun7i-a20-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ccu RST_TCON0>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD0>,
				 <&ccu CLK_TCON0_CH0>,
				 <&ccu CLK_TCON0_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon0-pixel-clock";
			dmas = <&dma SUN4I_DMA_DEDICATED 14>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon0_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon0>;
					};

					tcon0_in_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon0_out_hdmi: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&hdmi_in_tcon0>;
						allwinner,tcon-channel = <1>;
					};
				};
			};
		};

		tcon1: lcd-controller@1c0d000 {
			compatible = "allwinner,sun7i-a20-tcon";
			reg = <0x01c0d000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ccu RST_TCON1>;
			reset-names = "lcd";
			clocks = <&ccu CLK_AHB_LCD1>,
				 <&ccu CLK_TCON1_CH0>,
				 <&ccu CLK_TCON1_CH1>;
			clock-names = "ahb",
				      "tcon-ch0",
				      "tcon-ch1";
			clock-output-names = "tcon1-pixel-clock";
			dmas = <&dma SUN4I_DMA_DEDICATED 15>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon1_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					tcon1_in_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_out_tcon1>;
					};

					tcon1_in_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_out_tcon1>;
					};
				};

				tcon1_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					tcon1_out_hdmi: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&hdmi_in_tcon1>;
						allwinner,tcon-channel = <1>;
					};
				};
			};
		};

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		mmc0: mmc@1c0f000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c0f000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc1: mmc@1c10000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c10000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc2: mmc@1c11000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c11000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC2>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		mmc3: mmc@1c12000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c12000 0x1000>;
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			clocks = <&ccu CLK_AHB_MMC3>,
				 <&ccu CLK_MMC3>,
				 <&ccu CLK_MMC3_OUTPUT>,
				 <&ccu CLK_MMC3_SAMPLE>;
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			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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		usb_otg: usb@1c13000 {
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			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
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			clocks = <&ccu CLK_AHB_OTG>;
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			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

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		usbphy: phy@1c13400 {
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			#phy-cells = <1>;
			compatible = "allwinner,sun7i-a20-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
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			clocks = <&ccu CLK_USB_PHY>;
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			clock-names = "usb_phy";
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			resets = <&ccu RST_USB_PHY0>,
				 <&ccu RST_USB_PHY1>,
				 <&ccu RST_USB_PHY2>;
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			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
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			status = "disabled";
		};

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		ehci0: usb@1c14000 {
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			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
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			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_EHCI0>;
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			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

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		ohci0: usb@1c14400 {
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			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
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			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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563
			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
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			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

569
		crypto: crypto-engine@1c15000 {
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			compatible = "allwinner,sun7i-a20-crypto",
				     "allwinner,sun4i-a10-crypto";
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			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
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			clock-names = "ahb", "mod";
		};

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		hdmi: hdmi@1c16000 {
			compatible = "allwinner,sun7i-a20-hdmi",
				     "allwinner,sun5i-a10s-hdmi";
			reg = <0x01c16000 0x1000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
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				 <&ccu CLK_PLL_VIDEO0_2X>,
				 <&ccu CLK_PLL_VIDEO1_2X>;
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			clock-names = "ahb", "mod", "pll-0", "pll-1";
			dmas = <&dma SUN4I_DMA_NORMAL 16>,
			       <&dma SUN4I_DMA_NORMAL 16>,
			       <&dma SUN4I_DMA_DEDICATED 24>;
			dma-names = "ddc-tx", "ddc-rx", "audio-tx";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				hdmi_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					hdmi_in_tcon0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&tcon0_out_hdmi>;
					};

					hdmi_in_tcon1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&tcon1_out_hdmi>;
					};
				};

				hdmi_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

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		spi2: spi@1c17000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
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			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
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			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <1>;
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		};

636
		ahci: sata@1c18000 {
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			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
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			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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640
			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
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			status = "disabled";
		};

644
		ehci1: usb@1c1c000 {
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			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
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			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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648
			clocks = <&ccu CLK_AHB_EHCI1>;
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			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

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		ohci1: usb@1c1c400 {
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			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
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			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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658
			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
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			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

664
		spi3: spi@1c1f000 {
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			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
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			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
669
			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
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			dma-names = "rx", "tx";
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <1>;
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		};

679
		ccu: clock@1c20000 {
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			compatible = "allwinner,sun7i-a20-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

688
		pio: pinctrl@1c20800 {
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			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
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			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
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			clock-names = "apb", "hosc", "losc";
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			gpio-controller;
			interrupt-controller;
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			#interrupt-cells = <3>;
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			#gpio-cells = <3>;
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			can0_pins_a: can0@0 {
				pins = "PH20", "PH21";
				function = "can";
			};

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			clk_out_a_pins_a: clk_out_a@0 {
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				pins = "PI12";
				function = "clk_out_a";
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			};

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			clk_out_b_pins_a: clk_out_b@0 {
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				pins = "PI13";
				function = "clk_out_b";
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			};

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			emac_pins_a: emac0@0 {
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				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "emac";
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			};

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			gmac_pins_mii_a: gmac_mii@0 {
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				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "gmac";
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			};

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			gmac_pins_rgmii_a: gmac_rgmii@0 {
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				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				        "PA7", "PA8", "PA10",
				       "PA11", "PA12", "PA13",
				       "PA15", "PA16";
				function = "gmac";
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				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
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				drive-strength = <40>;
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			};

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			i2c0_pins_a: i2c0@0 {
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				pins = "PB0", "PB1";
				function = "i2c0";
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			};

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			i2c1_pins_a: i2c1@0 {
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				pins = "PB18", "PB19";
				function = "i2c1";
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			};

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			i2c2_pins_a: i2c2@0 {
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				pins = "PB20", "PB21";
				function = "i2c2";
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			};

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			i2c3_pins_a: i2c3@0 {
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				pins = "PI0", "PI1";
				function = "i2c3";
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			};

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			ir0_rx_pins_a: ir0@0 {
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				pins = "PB4";
				function = "ir0";
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			};

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			ir0_tx_pins_a: ir0@1 {
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				pins = "PB3";
				function = "ir0";
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			};
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			ir1_rx_pins_a: ir1@0 {
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				pins = "PB23";
				function = "ir1";
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			};

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			ir1_tx_pins_a: ir1@1 {
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				pins = "PB22";
				function = "ir1";
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			};

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			mmc0_pins_a: mmc0@0 {
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				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
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				bias-pull-up;
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			};

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			mmc2_pins_a: mmc2@0 {
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				pins = "PC6", "PC7", "PC8",
				       "PC9", "PC10", "PC11";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
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			};

			mmc3_pins_a: mmc3@0 {
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				pins = "PI4", "PI5", "PI6",
				       "PI7", "PI8", "PI9";
				function = "mmc3";
				drive-strength = <30>;
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				bias-pull-up;
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			};

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			ps20_pins_a: ps20@0 {
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				pins = "PI20", "PI21";
				function = "ps2";
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			};
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			ps21_pins_a: ps21@0 {
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				pins = "PH12", "PH13";
				function = "ps2";
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			};

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			pwm0_pins_a: pwm0@0 {
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				pins = "PB2";
				function = "pwm";
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			};
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			pwm1_pins_a: pwm1@0 {
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				pins = "PI3";
				function = "pwm";
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			};

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			spdif_tx_pins_a: spdif@0 {
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				pins = "PB13";
				function = "spdif";
				bias-pull-up;
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			};
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			spi0_pins_a: spi0@0 {
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				pins = "PI11", "PI12", "PI13";
				function = "spi0";
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			};

			spi0_cs0_pins_a: spi0_cs0@0 {
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				pins = "PI10";
				function = "spi0";
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			};

			spi0_cs1_pins_a: spi0_cs1@0 {
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				pins = "PI14";
				function = "spi0";
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			};

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			spi1_pins_a: spi1@0 {
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				pins = "PI17", "PI18", "PI19";
				function = "spi1";
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			};

			spi1_cs0_pins_a: spi1_cs0@0 {
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				pins = "PI16";
				function = "spi1";
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			};

			spi2_pins_a: spi2@0 {
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				pins = "PC20", "PC21", "PC22";
				function = "spi2";
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			};

			spi2_pins_b: spi2@1 {
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				pins = "PB15", "PB16", "PB17";
				function = "spi2";
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			};

			spi2_cs0_pins_a: spi2_cs0@0 {
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				pins = "PC19";
				function = "spi2";
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			};

			spi2_cs0_pins_b: spi2_cs0@1 {
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				pins = "PB14";
				function = "spi2";
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			};
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			uart0_pins_a: uart0@0 {
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				pins = "PB22", "PB23";
				function = "uart0";
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			};

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			uart2_pins_a: uart2@0 {
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				pins = "PI16", "PI17", "PI18", "PI19";
				function = "uart2";
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			};
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			uart3_pins_a: uart3@0 {
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				pins = "PG6", "PG7", "PG8", "PG9";
				function = "uart3";
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			};

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			uart3_pins_b: uart3@1 {
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				pins = "PH0", "PH1";
				function = "uart3";
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			};

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			uart4_pins_a: uart4@0 {
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				pins = "PG10", "PG11";
				function = "uart4";
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			};

906
			uart4_pins_b: uart4@1 {
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				pins = "PH4", "PH5";
				function = "uart4";
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			};
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			uart5_pins_a: uart5@0 {
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				pins = "PI10", "PI11";
				function = "uart5";
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			};

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			uart6_pins_a: uart6@0 {
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				pins = "PI12", "PI13";
				function = "uart6";
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			};
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			uart7_pins_a: uart7@0 {
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				pins = "PI20", "PI21";
				function = "uart7";
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			};
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		};

927
		timer@1c20c00 {
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			compatible = "allwinner,sun4i-a10-timer";
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			reg = <0x01c20c00 0x90>;
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			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&osc24M>;
		};

939
		wdt: watchdog@1c20c90 {
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			compatible = "allwinner,sun4i-a10-wdt";
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			reg = <0x01c20c90 0x10>;
		};

944
		rtc: rtc@1c20d00 {
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			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
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			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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		};

950
		pwm: pwm@1c20e00 {
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			compatible = "allwinner,sun7i-a20-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

958
		spdif: spdif@1c21000 {
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			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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963
			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
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			clock-names = "apb", "spdif";
			dmas = <&dma SUN4I_DMA_NORMAL 2>,
			       <&dma SUN4I_DMA_NORMAL 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

971
		ir0: ir@1c21800 {
972
			compatible = "allwinner,sun4i-a10-ir";
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			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
974
			clock-names = "apb", "ir";
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			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

980
		ir1: ir@1c21c00 {
981
			compatible = "allwinner,sun4i-a10-ir";
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982
			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
983
			clock-names = "apb", "ir";
984
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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			reg = <0x01c21c00 0x40>;
			status = "disabled";
		};

989
		i2s1: i2s@1c22000 {
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			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-i2s";
			reg = <0x01c22000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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994
			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
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			clock-names = "apb", "mod";
			dmas = <&dma SUN4I_DMA_NORMAL 4>,
			       <&dma SUN4I_DMA_NORMAL 4>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1002
		i2s0: i2s@1c22400 {
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			#sound-dai-cells = <0>;
			compat