sun7i-a20.dtsi 40.6 KB
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/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
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 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
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 *
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 *  a) This file is free software; you can redistribute it and/or
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 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
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 *     This file is distributed in the hope that it will be useful,
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 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
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 */

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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/clock/sun4i-a10-pll2.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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/ {
	interrupt-parent = <&gic>;

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	aliases {
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		ethernet0 = &gmac;
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	};

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	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		framebuffer@0 {
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			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
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			allwinner,pipeline = "de_be0-lcd0-hdmi";
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			clocks = <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>, <&de_be0_clk>,
				 <&tcon0_ch1_clk>, <&dram_gates 26>;
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			status = "disabled";
		};
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		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
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			clocks = <&ahb_gates 36>, <&ahb_gates 44>,
				 <&de_be0_clk>, <&tcon0_ch0_clk>,
				 <&dram_gates 26>;
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			status = "disabled";
		};

		framebuffer@2 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-tve0";
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			clocks = <&ahb_gates 34>, <&ahb_gates 36>,
				 <&ahb_gates 44>,
				 <&de_be0_clk>, <&tcon0_ch1_clk>,
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				 <&dram_gates 5>, <&dram_gates 26>;
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			status = "disabled";
		};
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	};

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	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

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		cpu0: cpu@0 {
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			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
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			clocks = <&cpu>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
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				/* kHz	  uV */
				960000	1400000
				912000	1400000
				864000	1300000
				720000	1200000
				528000	1100000
				312000	1000000
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				144000	1000000
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				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
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			cooling-max-level = <6>;
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		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};
	};

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	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

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	memory {
		reg = <0x40000000 0x80000000>;
	};

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	timer {
		compatible = "arm,armv7-timer";
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		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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	};

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	pmu {
		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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	};

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	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		osc24M: clk@01c20050 {
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			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-osc-clk";
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			reg = <0x01c20050 0x4>;
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			clock-frequency = <24000000>;
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			clock-output-names = "osc24M";
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		};

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		osc3M: osc3M_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <8>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc3M";
		};

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		osc32k: clk@0 {
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			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
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			clock-output-names = "osc32k";
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		};
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		pll1: clk@01c20000 {
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			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-pll1-clk";
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			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
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			clock-output-names = "pll1";
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		};

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		pll2: clk@01c20008 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll2-clk";
			reg = <0x01c20008 0x8>;
			clocks = <&osc24M>;
			clock-output-names = "pll2-1x", "pll2-2x",
					     "pll2-4x", "pll2-8x";
		};

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		pll3: clk@01c20010 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20010 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll3";
		};

		pll3x2: pll3x2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
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			clocks = <&pll3>;
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			clock-div = <1>;
			clock-mult = <2>;
			clock-output-names = "pll3-2x";
		};

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		pll4: clk@01c20018 {
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			#clock-cells = <0>;
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			compatible = "allwinner,sun7i-a20-pll4-clk";
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			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
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			clock-output-names = "pll4";
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		};

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		pll5: clk@01c20020 {
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			#clock-cells = <1>;
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			compatible = "allwinner,sun4i-a10-pll5-clk";
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			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

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		pll6: clk@01c20028 {
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			#clock-cells = <1>;
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			compatible = "allwinner,sun4i-a10-pll6-clk";
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			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
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			clock-output-names = "pll6_sata", "pll6_other", "pll6",
					     "pll6_div_4";
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		};

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		pll7: clk@01c20030 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll3-clk";
			reg = <0x01c20030 0x4>;
			clocks = <&osc3M>;
			clock-output-names = "pll7";
		};

		pll7x2: pll7x2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
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			clocks = <&pll7>;
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			clock-div = <1>;
			clock-mult = <2>;
			clock-output-names = "pll7-2x";
		};

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		pll8: clk@01c20040 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-pll4-clk";
			reg = <0x01c20040 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll8";
		};

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		cpu: cpu@01c20054 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-cpu-clk";
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			reg = <0x01c20054 0x4>;
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			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
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			clock-output-names = "cpu";
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		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-axi-clk";
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			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
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			clock-output-names = "axi";
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		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun5i-a13-ahb-clk";
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			reg = <0x01c20054 0x4>;
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			clocks = <&axi>, <&pll6 3>, <&pll6 1>;
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			clock-output-names = "ahb";
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			/*
			 * Use PLL6 as parent, instead of CPU/AXI
			 * which has rate changes due to cpufreq
			 */
			assigned-clocks = <&ahb>;
			assigned-clock-parents = <&pll6 3>;
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		};

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		ahb_gates: clk@01c20060 {
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			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
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			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>, <8>,
					<9>, <10>, <11>, <12>,
					<13>, <14>, <16>,
					<17>, <18>, <20>, <21>,
					<22>, <23>, <25>,
					<28>, <32>, <33>, <34>,
					<35>, <36>, <37>, <40>,
					<41>, <42>, <43>,
					<44>, <45>, <46>,
					<47>, <49>, <50>,
					<52>;
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			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
				"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
				"ahb_nand", "ahb_sdram", "ahb_ace",
				"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
				"ahb_spi2", "ahb_spi3", "ahb_sata",
				"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
				"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
				"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_gmac", "ahb_mp",
				"ahb_mali";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-apb0-clk";
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			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
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			clock-output-names = "apb0";
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		};

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		apb0_gates: clk@01c20068 {
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			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
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			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>,
					<8>, <10>;
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			clock-output-names = "apb0_codec", "apb0_spdif",
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				"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
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				"apb0_pio", "apb0_ir0", "apb0_ir1",
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				"apb0_i2s2", "apb0_keypad";
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		};

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		apb1: clk@01c20058 {
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			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-apb1-clk";
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			reg = <0x01c20058 0x4>;
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			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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			clock-output-names = "apb1";
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		};

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		apb1_gates: clk@01c2006c {
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			#clock-cells = <1>;
			compatible = "allwinner,sun7i-a20-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
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			clock-indices = <0>, <1>,
					<2>, <3>, <4>,
					<5>, <6>, <7>,
					<15>, <16>, <17>,
					<18>, <19>, <20>,
					<21>, <22>, <23>;
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			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_i2c3", "apb1_can",
				"apb1_scr", "apb1_ps20", "apb1_ps21",
				"apb1_i2c4", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3", "apb1_uart4",
				"apb1_uart5", "apb1_uart6", "apb1_uart7";
		};
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		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
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			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
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			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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			clock-output-names = "mmc0",
					     "mmc0_output",
					     "mmc0_sample";
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		};

		mmc1_clk: clk@01c2008c {
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			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
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			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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			clock-output-names = "mmc1",
					     "mmc1_output",
					     "mmc1_sample";
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		};

		mmc2_clk: clk@01c20090 {
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			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
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			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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			clock-output-names = "mmc2",
					     "mmc2_output",
					     "mmc2_sample";
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		};

		mmc3_clk: clk@01c20094 {
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			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-mmc-clk";
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			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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			clock-output-names = "mmc3",
					     "mmc3_output",
					     "mmc3_sample";
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		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

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		i2s0_clk: clk@01c200b8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200b8 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "i2s0";
		};

		ac97_clk: clk@01c200bc {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200bc 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "ac97";
		};

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		spdif_clk: clk@01c200c0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200c0 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "spdif";
		};

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		keypad_clk: clk@01c200c4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200c4 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "keypad";
		};

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		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
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			#reset-cells = <1>;
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			compatible = "allwinner,sun4i-a10-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
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			clock-output-names = "usb_ohci0", "usb_ohci1",
					     "usb_phy";
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		};

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		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
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			compatible = "allwinner,sun4i-a10-mod0-clk";
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			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};
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		i2s1_clk: clk@01c200d8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200d8 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "i2s1";
		};

		i2s2_clk: clk@01c200dc {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod1-clk";
			reg = <0x01c200dc 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_8X>,
				 <&pll2 SUN4I_A10_PLL2_4X>,
				 <&pll2 SUN4I_A10_PLL2_2X>,
				 <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "i2s2";
		};

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		dram_gates: clk@01c20100 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-dram-gates-clk";
			reg = <0x01c20100 0x4>;
			clocks = <&pll5 0>;
			clock-indices = <0>,
					<1>, <2>,
					<3>,
					<4>,
					<5>, <6>,
					<15>,
					<24>, <25>,
					<26>, <27>,
					<28>, <29>;
			clock-output-names = "dram_ve",
					     "dram_csi0", "dram_csi1",
					     "dram_ts",
					     "dram_tvd",
					     "dram_tve0", "dram_tve1",
					     "dram_output",
					     "dram_de_fe1", "dram_de_fe0",
					     "dram_de_be0", "dram_de_be1",
					     "dram_de_mp", "dram_ace";
		};

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		de_be0_clk: clk@01c20104 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20104 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-be0";
		};

		de_be1_clk: clk@01c20108 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20108 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-be1";
		};

		de_fe0_clk: clk@01c2010c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c2010c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-fe0";
		};

		de_fe1_clk: clk@01c20110 {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-display-clk";
			reg = <0x01c20110 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll5 1>;
			clock-output-names = "de-fe1";
		};

		tcon0_ch0_clk: clk@01c20118 {
			#clock-cells = <0>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
			reg = <0x01c20118 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon0-ch0-sclk";

		};

		tcon1_ch0_clk: clk@01c2011c {
			#clock-cells = <0>;
			#reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
			reg = <0x01c2011c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon1-ch0-sclk";

		};

		tcon0_ch1_clk: clk@01c2012c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
			reg = <0x01c2012c 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon0-ch1-sclk";

		};

		tcon1_ch1_clk: clk@01c20130 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
			reg = <0x01c20130 0x4>;
			clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
			clock-output-names = "tcon1-ch1-sclk";

		};

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		ve_clk: clk@01c2013c {
			#clock-cells = <0>;
			#reset-cells = <0>;
			compatible = "allwinner,sun4i-a10-ve-clk";
			reg = <0x01c2013c 0x4>;
			clocks = <&pll4>;
			clock-output-names = "ve";
		};

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		codec_clk: clk@01c20140 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-codec-clk";
			reg = <0x01c20140 0x4>;
			clocks = <&pll2 SUN4I_A10_PLL2_1X>;
			clock-output-names = "codec";
		};

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		mbus_clk: clk@01c2015c {
			#clock-cells = <0>;
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			compatible = "allwinner,sun5i-a13-mbus-clk";
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			reg = <0x01c2015c 0x4>;
			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
			clock-output-names = "mbus";
		};
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		/*
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		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
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		 */
		mii_phy_tx_clk: clk@2 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: clk@3 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@01c20164 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x01c20164 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

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		/*
		 * Dummy clock used by output clocks
		 */
		osc24M_32k: clk@1 {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <750>;
			clock-mult = <1>;
			clocks = <&osc24M>;
			clock-output-names = "osc24M_32k";
		};

		clk_out_a: clk@01c201f0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f0 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_a";
		};

		clk_out_b: clk@01c201f4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-out-clk";
			reg = <0x01c201f4 0x4>;
			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
			clock-output-names = "clk_out_b";
		};
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	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

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		sram-controller@01c00000 {
			compatible = "allwinner,sun4i-a10-sram-controller";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_a: sram@00000000 {
				compatible = "mmio-sram";
				reg = <0x00000000 0xc000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00000000 0xc000>;

				emac_sram: sram-section@8000 {
					compatible = "allwinner,sun4i-a10-sram-a3-a4";
					reg = <0x8000 0x4000>;
					status = "disabled";
				};
			};

			sram_d: sram@00010000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0000 {
					compatible = "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

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		nmi_intc: interrupt-controller@01c00030 {
			compatible = "allwinner,sun7i-a20-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01c00030 0x0c>;
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			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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		};

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		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
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			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

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		nfc: nand@01c03000 {
			compatible = "allwinner,sun4i-a10-nand";
			reg = <0x01c03000 0x1000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahb_gates 13>, <&nand_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
			dma-names = "rxtx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
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			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <4>;
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		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
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			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
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			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
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			dma-names = "rx", "tx";
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			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
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			num-cs = <1>;
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		};

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		emac: ethernet@01c0b000 {
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			compatible = "allwinner,sun4i-a10-emac";
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			reg = <0x01c0b000 0x1000>;
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			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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			clocks = <&ahb_gates 17>;
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			allwinner,sram = <&emac_sram 1>;
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			status = "disabled";
		};

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		mdio: mdio@01c0b080 {
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			compatible = "allwinner,sun4i-a10-mdio";
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			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

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		mmc0: mmc@01c0f000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c0f000 0x1000>;
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			clocks = <&ahb_gates 8>,
				 <&mmc0_clk 0>,
				 <&mmc0_clk 1>,
				 <&mmc0_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

		mmc1: mmc@01c10000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c10000 0x1000>;
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			clocks = <&ahb_gates 9>,
				 <&mmc1_clk 0>,
				 <&mmc1_clk 1>,
				 <&mmc1_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

		mmc2: mmc@01c11000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c11000 0x1000>;
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			clocks = <&ahb_gates 10>,
				 <&mmc2_clk 0>,
				 <&mmc2_clk 1>,
				 <&mmc2_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

		mmc3: mmc@01c12000 {
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			compatible = "allwinner,sun7i-a20-mmc";
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			reg = <0x01c12000 0x1000>;
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			clocks = <&ahb_gates 11>,
				 <&mmc3_clk 0>,
				 <&mmc3_clk 1>,
				 <&mmc3_clk 2>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
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			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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			status = "disabled";
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			#address-cells = <1>;
			#size-cells = <0>;
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		};

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983
984
985
986
987
988
		usb_otg: usb@01c13000 {
			compatible = "allwinner,sun4i-a10-musb";
			reg = <0x01c13000 0x0400>;
			clocks = <&ahb_gates 0>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			allwinner,sram = <&otg_sram 1>;
			status = "disabled";
		};

989
990
991
992
993
994
995
		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun7i-a20-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
996
997
			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
998
999
1000
1001
1002
1003
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
1004
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1005
1006
1007
1008
1009
1010
1011
1012
1013
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
1014
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1015
1016
1017
1018
1019
1020
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

1021
1022
1023
1024
1025
1026
1027
1028
		crypto: crypto-engine@01c15000 {
			compatible = "allwinner,sun4i-a10-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ahb_gates 5>, <&ss_clk>;
			clock-names = "ahb", "mod";
		};

1029
1030
1031
		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
1032
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1033
1034
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
1035
1036
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
1037
			dma-names = "rx", "tx";
1038
1039
1040
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
1041
			num-cs = <1>;
1042
1043
		};

1044
1045
1046
		ahci: sata@01c18000 {
			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
1047
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1048
1049
1050
1051
			clocks = <&pll6 0>, <&ahb_gates 25>;
			status = "disabled";
		};

1052
1053
1054
		ehci1: usb@01c1c000 {
			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
1055
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1056
1057
1058
1059
1060
1061
1062
1063
1064
			clocks = <&ahb_gates 3>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1c400 {
			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
1065
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1066
1067
1068
1069
1070
1071
			clocks = <&usb_clk 7>, <&ahb_gates 4>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

1072
1073
1074
		spi3: spi@01c1f000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
1075
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1076
1077
			clocks = <&ahb_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
1078
1079
			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
1080
			dma-names = "rx", "tx";
1081
			status = "disabled";
1082
1083
			#address-cells = <1>;
			#size-cells = <0>;
1084
			num-cs = <1>;
1085
1086
		};

1087
1088
1089
		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun7i-a20-pinctrl";
			reg = <0x01c20800 0x400>;
1090
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1091
1092
			clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
1093
1094
			gpio-controller;
			interrupt-controller;
1095
			#interrupt-cells = <3>;
1096
			#gpio-cells = <3>;
1097

1098
			clk_out_a_pins_a: clk_out_a@0 {
1099
1100
				pins = "PI12";
				function = "clk_out_a";
1101
1102
			};

1103
			clk_out_b_pins_a: clk_out_b@0 {
1104
1105
				pins = "PI13";
				function = "clk_out_b";
1106
1107
			};

1108
			emac_pins_a: emac0@0 {
1109
1110
1111
1112
1113
1114
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "emac";
1115
1116
			};

1117
			gmac_pins_mii_a: gmac_mii@0 {
1118
1119
1120
1121
1122
1123
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				       "PA7", "PA8", "PA9", "PA10",
				       "PA11", "PA12", "PA13", "PA14",
				       "PA15", "PA16";
				function = "gmac";
1124
1125
			};

1126
			gmac_pins_rgmii_a: gmac_rgmii@0 {
1127
1128
1129
1130
1131
1132
				pins = "PA0", "PA1", "PA2",
				       "PA3", "PA4", "PA5", "PA6",
				        "PA7", "PA8", "PA10",
				       "PA11", "PA12", "PA13",
				       "PA15", "PA16";
				function = "gmac";
1133
1134
1135
1136
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
1137
				drive-strength = <40>;
1138
1139
			};

1140
			i2c0_pins_a: i2c0@0 {
1141
1142
				pins = "PB0", "PB1";
				function = "i2c0";
1143
1144
			};

1145
			i2c1_pins_a: i2c1@0 {
1146
1147
				pins = "PB18", "PB19";
				function = "i2c1";
1148
1149
			};

1150
			i2c2_pins_a: i2c2@0 {
1151
1152
				pins = "PB20", "PB21";
				function = "i2c2";
1153
1154
			};

1155
			i2c3_pins_a: i2c3@0 {
1156
1157
				pins = "PI0", "PI1";
				function = "i2c3";
1158
1159
			};

1160
			ir0_rx_pins_a: ir0@0 {
1161
1162
				pins = "PB4";
				function = "ir0";
1163
1164
			};

1165
			ir0_tx_pins_a: ir0@1 {
1166
1167
				pins = "PB3";
				function = "ir0";
1168
			};
1169

1170
			ir1_rx_pins_a: ir1@0 {
1171
1172
				pins = "PB23";
				function = "ir1";
1173
1174
			};

1175
			ir1_tx_pins_a: ir1@1 {
1176
1177
				pins = "PB22";
				function = "ir1";
1178
1179
			};

1180
			mmc0_pins_a: mmc0@0 {
1181
1182
1183
1184
				pins = "PF0", "PF1", "PF2",
				       "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
1185
				bias-pull-up;
1186
1187
			};

1188
			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1189
1190
1191
				pins = "PH1";
				function = "gpio_in";
				bias-pull-up;
1192
1193
1194
			};

			mmc2_pins_a: mmc2@0 {
1195
1196
1197
1198
1199
				pins = "PC6", "PC7", "PC8",
				       "PC9", "PC10", "PC11";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
1200
1201
1202
			};

			mmc3_pins_a: mmc3@0 {
1203
1204
1205
1206
				pins = "PI4", "PI5", "PI6",
				       "PI7", "PI8", "PI9";
				function = "mmc3";
				drive-strength = <30>;
1207
				bias-pull-up;
1208
1209
			};

1210
			ps20_pins_a: ps20@0 {
1211
1212
				pins = "PI20", "PI21";
				function = "ps2";
1213
			};
1214

1215
			ps21_pins_a: ps21@0 {
1216
1217
				pins = "PH12", "PH13";
				function = "ps2";
1218
1219
			};

1220
			pwm0_pins_a: pwm0@0 {
1221
1222
				pins = "PB2";
				function = "pwm";
1223
			};
1224

1225
			pwm1_pins_a: pwm1@0 {
1226
1227
				pins = "PI3";
				function = "pwm";
1228
1229
			};

1230
			spdif_tx_pins_a: spdif@0 {
1231
1232
1233
				pins = "PB13";
				function = "spdif";
				bias-pull-up;
1234
			};
1235

1236
			spi0_pins_a: spi0@0 {
1237
1238
				pins = "PI11", "PI12", "PI13";
				function = "spi0";
1239
1240
1241
			};

			spi0_cs0_pins_a: spi0_cs0@0 {
1242
1243
				pins = "PI10";
				function = "spi0";
1244
1245
1246
			};

			spi0_cs1_pins_a: spi0_cs1@0 {
1247
1248
				pins = "PI14";
				function = "spi0";
1249
1250
			};

1251
			spi1_pins_a: spi1@0 {
1252
1253
				pins = "PI17", "PI18", "PI19";
				function = "spi1";
1254
1255
1256
			};

			spi1_cs0_pins_a: spi1_cs0@0 {
1257
1258
				pins = "PI16";
				function = "spi1";
1259
1260
1261
			};

			spi2_pins_a: spi2@0 {
1262
1263
				pins = "PC20", "PC21", "PC22";
				function = "spi2";
1264
1265
1266
			};

			spi2_pins_b: spi2@1 {
1267
1268
				pins = "PB15", "PB16", "PB17";
				function = "spi2";
1269
1270
1271
			};

			spi2_cs0_pins_a: spi2_cs0@0 {
1272
1273
				pins = "PC19";
				function = "spi2";
1274
1275
1276
			};

			spi2_cs0_pins_b: spi2_cs0@1 {
1277
1278
				pins = "PB14";
				function = "spi2";
1279
			};
1280

1281
			uart0_pins_a: uart0@0 {
1282
1283
				pins = "PB22", "PB23";
				function = "uart0";
1284
1285
			};

1286
			uart2_pins_a: uart2@0 {
1287
1288
				pins = "PI16", "PI17", "PI18", "PI19";
				function = "uart2";
1289
			};
1290

1291
			uart3_pins_a: uart3@0 {
1292
1293
				pins = "PG6", "PG7", "PG8", "PG9";
				function = "uart3";
1294
1295
			};

1296
			uart3_pins_b: uart3@1 {
1297
1298
				pins = "PH0", "PH1";
				function = "uart3";
1299
1300
			};

1301
			uart4_pins_a: uart4@0 {
1302
1303
				pins = "PG10", "PG11";
				function = "uart4";
1304
1305
			};

1306
			uart4_pins_b: uart4@1 {
1307
1308
				pins = "PH4", "PH5";
				function = "uart4";
1309
			};
1310

1311
			uart5_pins_a: uart5@0 {
1312
1313
				pins = "PI10", "PI11";
				function = "uart5";
1314
1315
			};

1316
			uart6_pins_a: uart6@0 {
1317
1318
				pins = "PI12", "PI13";
				function = "uart6";
1319
			};
1320

1321
			uart7_pins_a: uart7@0 {
1322
1323
				pins = "PI20", "PI21";
				function = "uart7";
1324
			};
1325
1326
		};

1327
		timer@01c20c00 {
1328
			compatible = "allwinner,sun4i-a10-timer";
1329
			reg = <0x01c20c00 0x90>;
1330
1331
1332
1333
1334
1335
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1336
1337
1338
1339
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
1340
			compatible = "allwinner,sun4i-a10-wdt";
1341
1342
1343
			reg = <0x01c20c90 0x10>;
		};

1344
1345
1346
		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun7i-a20-rtc";
			reg = <0x01c20d00 0x20>;
1347
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1348
1349
		};

1350
1351
1352
1353
1354
1355
1356
1357
		pwm: pwm@01c20e00 {
			compatible = "allwinner,sun7i-a20-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
		spdif: spdif@01c21000 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun4i-a10-spdif";
			reg = <0x01c21000 0x400>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb0_gates 1>, <&spdif_clk>;
			clock-names = "apb", "spdif";
			dmas = <&dma SUN4I_DMA_NORMAL 2>,
			       <&dma SUN4I_DMA_NORMAL 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

1371
		ir0: ir@01c21800 {
1372
			compatible = "allwinner,sun4i-a10-ir";
1373
1374
			clocks = <&apb0_gates 6>, <&ir0_clk>;
			clock-names = "apb", "ir";
1375
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1376
1377
1378
1379
1380
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

		ir1: ir@01c21c00 {
1381
			compatible = "allwinner,sun4i-a10-ir";
1382
1383
			clocks = <&apb0_gates 7>, <&ir1_clk>;
			clock-names = "apb", "ir";
1384
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1385
1386
1387
1388