Commit 0261b5d3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu updates from Greg Ungerer:
 "There are two sets of changes in this pull.

  The largest is the addition of the ColdFire platform side i2c support
  (the IO addressing, setup and clock definitions). The i2c hardware
  module itself is driven by the kernels existing iMX i2c driver.

  The other change is the addition of support for the Amcore board"

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: AMCORE board, add iMX i2c support
  m68k: add Sysam AMCORE open board support
  m68knommu: platform support for i2c devices on ColdFire SoC
parents 067d14f0 07c65a66
......@@ -259,6 +259,12 @@ config M5407C3
help
Support for the Motorola M5407C3 board.
config AMCORE
bool "Sysam AMCORE board support"
depends on M5307
help
Support for the Sysam AMCORE open-hardware generic board.
config FIREBEE
bool "FireBee board support"
depends on M547x
......
......@@ -34,6 +34,7 @@ obj-$(CONFIG_NETtel) += nettel.o
obj-$(CONFIG_CLEOPATRA) += nettel.o
obj-$(CONFIG_FIREBEE) += firebee.o
obj-$(CONFIG_MCF8390) += mcf8390.o
obj-$(CONFIG_AMCORE) += amcore.o
obj-$(CONFIG_PCI) += pci.o
......
/*
* amcore.c -- Support for Sysam AMCORE open board
*
* (C) Copyright 2016, Angelo Dureghello <angelo@sysam.it>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/io.h>
#if IS_ENABLED(CONFIG_DM9000)
#define DM9000_IRQ 25
#define DM9000_ADDR 0x30000000
/*
* DEVICES and related device RESOURCES
*/
static struct resource dm9000_resources[] = {
/* physical address of the address register (CMD [A2] to 0)*/
[0] = {
.start = DM9000_ADDR,
.end = DM9000_ADDR,
.flags = IORESOURCE_MEM,
},
/*
* physical address of the data register (CMD [A2] to 1),
* driver wants a range >=4 to assume a 32bit data bus
*/
[1] = {
.start = DM9000_ADDR + 4,
.end = DM9000_ADDR + 7,
.flags = IORESOURCE_MEM,
},
/* IRQ line the device's interrupt pin is connected to */
[2] = {
.start = DM9000_IRQ,
.end = DM9000_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct dm9000_plat_data dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_platdata,
}
};
#endif
static void __init dm9000_pre_init(void)
{
/* Set the dm9000 interrupt to be auto-vectored */
mcf_autovector(DM9000_IRQ);
}
/*
* Partitioning of parallel NOR flash (39VF3201B)
*/
static struct mtd_partition amcore_partitions[] = {
{
.name = "U-Boot (128K)",
.size = 0x20000,
.offset = 0x0
},
{
.name = "Kernel+ROMfs (2994K)",
.size = 0x2E0000,
.offset = MTDPART_OFS_APPEND
},
{
.name = "Flash Free Space (1024K)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct physmap_flash_data flash_data = {
.parts = amcore_partitions,
.nr_parts = ARRAY_SIZE(amcore_partitions),
.width = 2,
};
static struct resource flash_resource = {
.start = 0xffc00000,
.end = 0xffffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device rtc_device = {
.name = "rtc-ds1307",
.id = -1,
};
static struct i2c_board_info amcore_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("ds1338", 0x68),
},
};
static struct platform_device *amcore_devices[] __initdata = {
#if IS_ENABLED(CONFIG_DM9000)
&dm9000_device,
#endif
&flash_device,
&rtc_device,
};
static int __init init_amcore(void)
{
#if IS_ENABLED(CONFIG_DM9000)
dm9000_pre_init();
#endif
/* Add i2c RTC Dallas chip supprt */
i2c_register_board_info(0, amcore_i2c_info,
ARRAY_SIZE(amcore_i2c_info));
platform_add_devices(amcore_devices, ARRAY_SIZE(amcore_devices));
return 0;
}
arch_initcall(init_amcore);
......@@ -327,6 +327,147 @@ static struct platform_device mcf_qspi = {
};
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
#if IS_ENABLED(CONFIG_I2C_IMX)
static struct resource mcf_i2c0_resources[] = {
{
.start = MCFI2C_BASE0,
.end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C0,
.end = MCF_IRQ_I2C0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c0 = {
.name = "imx1-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_i2c0_resources),
.resource = mcf_i2c0_resources,
};
#ifdef MCFI2C_BASE1
static struct resource mcf_i2c1_resources[] = {
{
.start = MCFI2C_BASE1,
.end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C1,
.end = MCF_IRQ_I2C1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c1 = {
.name = "imx1-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(mcf_i2c1_resources),
.resource = mcf_i2c1_resources,
};
#endif /* MCFI2C_BASE1 */
#ifdef MCFI2C_BASE2
static struct resource mcf_i2c2_resources[] = {
{
.start = MCFI2C_BASE2,
.end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C2,
.end = MCF_IRQ_I2C2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c2 = {
.name = "imx1-i2c",
.id = 2,
.num_resources = ARRAY_SIZE(mcf_i2c2_resources),
.resource = mcf_i2c2_resources,
};
#endif /* MCFI2C_BASE2 */
#ifdef MCFI2C_BASE3
static struct resource mcf_i2c3_resources[] = {
{
.start = MCFI2C_BASE3,
.end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C3,
.end = MCF_IRQ_I2C3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c3 = {
.name = "imx1-i2c",
.id = 3,
.num_resources = ARRAY_SIZE(mcf_i2c3_resources),
.resource = mcf_i2c3_resources,
};
#endif /* MCFI2C_BASE3 */
#ifdef MCFI2C_BASE4
static struct resource mcf_i2c4_resources[] = {
{
.start = MCFI2C_BASE4,
.end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C4,
.end = MCF_IRQ_I2C4,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c4 = {
.name = "imx1-i2c",
.id = 4,
.num_resources = ARRAY_SIZE(mcf_i2c4_resources),
.resource = mcf_i2c4_resources,
};
#endif /* MCFI2C_BASE4 */
#ifdef MCFI2C_BASE5
static struct resource mcf_i2c5_resources[] = {
{
.start = MCFI2C_BASE5,
.end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C5,
.end = MCF_IRQ_I2C5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c5 = {
.name = "imx1-i2c",
.id = 5,
.num_resources = ARRAY_SIZE(mcf_i2c5_resources),
.resource = mcf_i2c5_resources,
};
#endif /* MCFI2C_BASE5 */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
static struct platform_device *mcf_devices[] __initdata = {
&mcf_uart,
#if IS_ENABLED(CONFIG_FEC)
......@@ -338,6 +479,24 @@ static struct platform_device *mcf_devices[] __initdata = {
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
&mcf_qspi,
#endif
#if IS_ENABLED(CONFIG_I2C_IMX)
&mcf_i2c0,
#ifdef MCFI2C_BASE1
&mcf_i2c1,
#endif
#ifdef MCFI2C_BASE2
&mcf_i2c2,
#endif
#ifdef MCFI2C_BASE3
&mcf_i2c3,
#endif
#ifdef MCFI2C_BASE4
&mcf_i2c4,
#endif
#ifdef MCFI2C_BASE5
&mcf_i2c5,
#endif
#endif
};
/*
......
......@@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
......@@ -34,11 +35,21 @@ struct clk *mcf_clks[] = {
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
};
/***************************************************************************/
static void __init m5206_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel)
......@@ -53,6 +64,7 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(28, MCFINTC_EINT4);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5206_i2c_init();
}
/***************************************************************************/
......@@ -28,7 +28,7 @@ DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
......@@ -53,7 +53,7 @@ struct clk *mcf_clks[] = {
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
......@@ -71,7 +71,7 @@ struct clk *mcf_clks[] = {
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* sdram.0 */
NULL,
NULL,
};
static struct clk * const enable_clks[] __initconst = {
......@@ -94,7 +94,7 @@ static struct clk * const enable_clks[] __initconst = {
static struct clk * const disable_clks[] __initconst = {
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
......@@ -133,6 +133,21 @@ static void __init m520x_qspi_init(void)
/***************************************************************************/
static void __init m520x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCF_GPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCF_GPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m520x_uarts_init(void)
{
u16 par;
......@@ -175,6 +190,7 @@ void __init config_BSP(char *commandp, int size)
m520x_uarts_init();
m520x_fec_init();
m520x_qspi_init();
m520x_i2c_init();
}
/***************************************************************************/
......@@ -34,6 +34,7 @@ DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
......@@ -47,6 +48,7 @@ struct clk *mcf_clks[] = {
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
};
......@@ -68,6 +70,21 @@ static void __init m523x_qspi_init(void)
/***************************************************************************/
static void __init m523x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m523x_fec_init(void)
{
/* Set multi-function pins to ethernet use */
......@@ -81,6 +98,7 @@ void __init config_BSP(char *commandp, int size)
mach_sched_init = hw_timer_init;
m523x_fec_init();
m523x_qspi_init();
m523x_i2c_init();
}
/***************************************************************************/
......@@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
......@@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
};
......@@ -85,6 +89,26 @@ static void __init m5249_qspi_init(void)
/***************************************************************************/
static void __init m5249_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* CONFIG_I2C_IMX */
}
/***************************************************************************/
#ifdef CONFIG_M5249C3
static void __init m5249_smc91x_init(void)
......@@ -111,6 +135,7 @@ void __init config_BSP(char *commandp, int size)
m5249_smc91x_init();
#endif
m5249_qspi_init();
m5249_i2c_init();
}
/***************************************************************************/
......
......@@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
......@@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
};
......@@ -59,12 +63,12 @@ static void __init m525x_qspi_init(void)
static void __init m525x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
......@@ -72,7 +76,7 @@ static void __init m525x_i2c_init(void)
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
......
......@@ -36,6 +36,7 @@ DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
......@@ -50,6 +51,7 @@ struct clk *mcf_clks[] = {
&clk_mcfqspi0,
&clk_fec0,
&clk_fec1,
&clk_mcfi2c0,
NULL
};
......@@ -76,6 +78,31 @@ static void __init m527x_qspi_init(void)
/***************************************************************************/
static void __init m527x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
#if defined(CONFIG_M5271)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#elif defined(CONFIG_M5275)
u16 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readw(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writew(par, MCFGPIO_PAR_FECI2C);
#endif
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m527x_uarts_init(void)