Commit c12e69c6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'staging-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging driver updates from Greg KH:
 "Here's the huge drivers/staging/ update for 3.15-rc1.

  Loads of cleanup fixes, a few drivers removed, and some new ones
  added.

  All have been in linux-next for a while"

* tag 'staging-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (1375 commits)
  staging: xillybus: XILLYBUS_PCIE depends on PCI_MSI
  staging: xillybus: Added "select CRC32" for XILLYBUS in Kconfig
  staging: comedi: poc: remove obsolete driver
  staging: unisys: replace kzalloc/kfree with UISMALLOC/UISFREE
  staging: octeon-usb: prevent memory corruption
  staging: usbip: fix line over 80 characters
  staging: usbip: fix quoted string split across lines
  Staging: unisys: Remove RETINT macro
  Staging: unisys: Remove FAIL macro
  Staging: unisys: Remove RETVOID macro
  Staging: unisys: Remove RETPTR macro
  Staging: unisys: Remove RETBOOL macro
  Staging: unisys: Remove FAIL_WPOSTCODE_1 macro
  Staging: unisys: Cleanup macros to get rid of goto statements
  Staging: unisys: include: Remove unused macros from timskmod.h
  staging: dgap: fix the rest of the checkpatch warnings in dgap.c
  Staging: bcm: Remove unnecessary parentheses
  staging: wlags49_h2: Delete unnecessary braces
  staging: wlags49_h2: Do not use assignment in if condition
  staging: wlags49_h2: Enclose macro in a do-while loop
  ...
parents 158e0d36 94debda3
......@@ -5,6 +5,9 @@ Required properties:
<chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5"
- reg: Should contain ADC registers location and length
- interrupts: Should contain the IRQ line for the ADC
- clock-names: tuple listing input clock names.
Required elements: "adc_clk", "adc_op_clk".
- clocks: phandles to input clocks.
- atmel,adc-channels-used: Bitmask of the channels muxed and enable for this
device
- atmel,adc-startup-time: Startup Time of the ADC in microseconds as
......@@ -44,6 +47,8 @@ adc0: adc@fffb0000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 4>;
clocks = <&adc_clk>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channel-base = <0x30>;
atmel,adc-channels-used = <0xff>;
atmel,adc-drdy-mask = <0x10000>;
......
Common bindings for device graphs
General concept
---------------
The hierarchical organisation of the device tree is well suited to describe
control flow to devices, but there can be more complex connections between
devices that work together to form a logical compound device, following an
arbitrarily complex graph.
There already is a simple directed graph between devices tree nodes using
phandle properties pointing to other nodes to describe connections that
can not be inferred from device tree parent-child relationships. The device
tree graph bindings described herein abstract more complex devices that can
have multiple specifiable ports, each of which can be linked to one or more
ports of other devices.
These common bindings do not contain any information about the direction or
type of the connections, they just map their existence. Specific properties
may be described by specialized bindings depending on the type of connection.
To see how this binding applies to video pipelines, for example, see
Documentation/device-tree/bindings/media/video-interfaces.txt.
Here the ports describe data interfaces, and the links between them are
the connecting data buses. A single port with multiple connections can
correspond to multiple devices being connected to the same physical bus.
Organisation of ports and endpoints
-----------------------------------
Ports are described by child 'port' nodes contained in the device node.
Each port node contains an 'endpoint' subnode for each remote device port
connected to this port. If a single port is connected to more than one
remote device, an 'endpoint' child node must be provided for each link.
If more than one port is present in a device node or there is more than one
endpoint at a port, or a port node needs to be associated with a selected
hardware interface, a common scheme using '#address-cells', '#size-cells'
and 'reg' properties is used number the nodes.
device {
...
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
endpoint@0 {
reg = <0>;
...
};
endpoint@1 {
reg = <1>;
...
};
};
port@1 {
reg = <1>;
endpoint { ... };
};
};
All 'port' nodes can be grouped under an optional 'ports' node, which
allows to specify #address-cells, #size-cells properties for the 'port'
nodes independently from any other child device nodes a device might
have.
device {
...
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
...
endpoint@0 { ... };
endpoint@1 { ... };
};
port@1 { ... };
};
};
Links between endpoints
-----------------------
Each endpoint should contain a 'remote-endpoint' phandle property that points
to the corresponding endpoint in the port of the remote device. In turn, the
remote endpoint should contain a 'remote-endpoint' property. If it has one,
it must not point to another than the local endpoint. Two endpoints with their
'remote-endpoint' phandles pointing at each other form a link between the
containing ports.
device-1 {
port {
device_1_output: endpoint {
remote-endpoint = <&device_2_input>;
};
};
};
device-2 {
port {
device_2_input: endpoint {
remote-endpoint = <&device_1_output>;
};
};
};
Required properties
-------------------
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
property is present in port and/or endpoint nodes the following properties
are required in a relevant parent node:
- #address-cells : number of cells required to define port/endpoint
identifier, should be 1.
- #size-cells : should be zero.
Optional endpoint properties
----------------------------
- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
Freescale vf610 Analog to Digital Converter bindings
The devicetree bindings are for the new ADC driver written for
vf610/i.MX6slx and upward SoCs from Freescale.
Required properties:
- compatible: Should contain "fsl,vf610-adc"
- reg: Offset and length of the register set for the device
- interrupts: Should contain the interrupt for the device
- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
- clock-names: Must contain "adc", matching entry in the clocks property.
- vref-supply: The regulator supply ADC refrence voltage.
Example:
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <0 53 0x04>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
vref-supply = <&reg_vcc_3v3_mcu>;
};
Xilinx XADC device driver
This binding document describes the bindings for both of them since the
bindings are very similar. The Xilinx XADC is a ADC that can be found in the
series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
Currently two different frontends for the DRP interface exist. One that is only
available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
other one is available on all series 7 platforms and is a softmacro with a AXI
interface. This binding document describes the bindings for both of them since
the bindings are very similar.
Required properties:
- compatible: Should be one of
* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
configuration interface to interface to the XADC hardmacro.
* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
interface to the XADC hardmacro.
- reg: Address and length of the register set for the device
- interrupts: Interrupt for the XADC control interface.
- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
when using the AXI-XADC pcore this must be the clock that provides the
clock to the AXI bus interface of the core.
Optional properties:
- interrupt-parent: phandle to the parent interrupt controller
- xlnx,external-mux:
* "none": No external multiplexer is used, this is the default
if the property is omitted.
* "single": External multiplexer mode is used with one
multiplexer.
* "dual": External multiplexer mode is used with two
multiplexers for simultaneous sampling.
- xlnx,external-mux-channel: Configures which pair of pins is used to
sample data in external mux mode.
Valid values for single external multiplexer mode are:
0: VP/VN
1: VAUXP[0]/VAUXN[0]
2: VAUXP[1]/VAUXN[1]
...
16: VAUXP[15]/VAUXN[15]
Valid values for dual external multiplexer mode are:
1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
...
8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
This property needs to be present if the device is configured for
external multiplexer mode (either single or dual). If the device is
not using external multiplexer mode the property is ignored.
- xnlx,channels: List of external channels that are connected to the ADC
Required properties:
* #address-cells: Should be 1.
* #size-cells: Should be 0.
The child nodes of this node represent the external channels which are
connected to the ADC. If the property is no present no external
channels will be assumed to be connected.
Each child node represents one channel and has the following
properties:
Required properties:
* reg: Pair of pins the the channel is connected to.
0: VP/VN
1: VAUXP[0]/VAUXN[0]
2: VAUXP[1]/VAUXN[1]
...
16: VAUXP[15]/VAUXN[15]
Note each channel number should only be used at most
once.
Optional properties:
* xlnx,bipolar: If set the channel is used in bipolar
mode.
Examples:
xadc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&gic>;
clocks = <&pcap_clk>;
xlnx,channels {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@8 {
reg = <8>;
};
};
};
xadc@43200000 {
compatible = "xlnx,axi-xadc-1.00.a";
reg = <0x43200000 0x1000>;
interrupts = <0 53 4>;
interrupt-parent = <&gic>;
clocks = <&fpga1_clk>;
xlnx,channels {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
xlnx,bipolar;
};
};
};
Freescale i.MX DRM master device
================================
The freescale i.MX DRM master device is a virtual device needed to list all
IPU or other display interface nodes that comprise the graphics subsystem.
Required properties:
- compatible: Should be "fsl,imx-display-subsystem"
- ports: Should contain a list of phandles pointing to display interface ports
of IPU devices
example:
display-subsystem {
compatible = "fsl,display-subsystem";
ports = <&ipu_di0>;
};
Freescale i.MX IPUv3
====================
......@@ -7,18 +26,31 @@ Required properties:
datasheet
- interrupts: Should contain sync interrupt and error interrupt,
in this order.
- #crtc-cells: 1, See below
- resets: phandle pointing to the system reset controller and
reset line index, see reset/fsl,imx-src.txt for details
Optional properties:
- port@[0-3]: Port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Ports 0 and 1 should correspond to CSI0 and CSI1,
ports 2 and 3 should correspond to DI0 and DI1, respectively.
example:
ipu: ipu@18000000 {
#crtc-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
resets = <&src 2>;
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp0: endpoint {
remote-endpoint = <&display_in>;
};
};
};
Parallel display support
......@@ -26,19 +58,25 @@ Parallel display support
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
- crtc: the crtc this display is connected to, see below
Optional properties:
- interface_pix_fmt: How this display is connected to the
crtc. Currently supported types: "rgb24", "rgb565", "bgr666"
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
channel
- port: A port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
example:
display@di0 {
compatible = "fsl,imx-parallel-display";
edid = [edid-data];
crtc = <&ipu 0>;
interface-pix-fmt = "rgb24";
port {
display_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
};
Device-Tree bindings for HDMI Transmitter
HDMI Transmitter
================
The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with accompanying PHY IP.
Required properties:
- #address-cells : should be <1>
- #size-cells : should be <0>
- compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
- gpr : should be <&gpr>.
The phandle points to the iomuxc-gpr region containing the HDMI
multiplexer control register.
- clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
- port@[0-4]: Up to four port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt,
corresponding to the four inputs to the HDMI multiplexer.
Optional properties:
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
example:
gpr: iomuxc-gpr@020e0000 {
/* ... */
};
hdmi: hdmi@0120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-hdmi";
reg = <0x00120000 0x9000>;
interrupts = <0 115 0x04>;
gpr = <&gpr>;
clocks = <&clks 123>, <&clks 124>;
clock-names = "iahb", "isfr";
ddc-i2c-bus = <&i2c2>;
port@0 {
reg = <0>;
hdmi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_hdmi>;
};
};
port@1 {
reg = <1>;
hdmi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_hdmi>;
};
};
};
......@@ -50,12 +50,14 @@ have a look at Documentation/devicetree/bindings/video/display-timing.txt.
Required properties:
- reg : should be <0> or <1>
- crtcs : a list of phandles with index pointing to the IPU display interfaces
that can be used as video source for this channel.
- fsl,data-mapping : should be "spwg" or "jeida"
This describes how the color bits are laid out in the
serialized LVDS signal.
- fsl,data-width : should be <18> or <24>
- port: A port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
On i.MX6, there should be four ports (port@[0-3]) that correspond
to the four LVDS multiplexer inputs.
example:
......@@ -77,23 +79,33 @@ ldb: ldb@53fa8008 {
lvds-channel@0 {
reg = <0>;
crtcs = <&ipu 0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {
/* ... */
};
port {
lvds0_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
};
};
};
lvds-channel@1 {
reg = <1>;
crtcs = <&ipu 1>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {
/* ... */
};
port {
lvds1_in: endpoint {
remote-endpoint = <&ipu_di1_lvds1>;
};
};
};
};
......@@ -8394,6 +8394,12 @@ M: Teddy Wang <teddy.wang@siliconmotion.com.cn>
S: Odd Fixes
F: drivers/staging/sm7xxfb/
STAGING - SLICOSS
M: Lior Dotan <liodot@gmail.com>
M: Christopher Harrer <charrer@alacritech.com>
S: Odd Fixes
F: drivers/staging/slicoss/
STAGING - SOFTLOGIC 6x10 MPEG CODEC
M: Ismael Luceno <ismael.luceno@corp.bluecherry.net>
S: Supported
......@@ -9079,6 +9085,13 @@ F: drivers/cdrom/cdrom.c
F: include/linux/cdrom.h
F: include/uapi/linux/cdrom.h
UNISYS S-PAR DRIVERS
M: Benjamin Romer <benjamin.romer@unisys.com>
M: David Kershner <david.kershner@unisys.com>
L: sparmaintainer@unisys.com (Unisys internal)
S: Supported
F: drivers/staging/unisys/
UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER
M: Vinayak Holikatti <vinholikatti@gmail.com>
M: Santosh Y <santoshsy@gmail.com>
......
......@@ -18,7 +18,6 @@
display@di1 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
......@@ -41,6 +40,12 @@
pixelclk-active = <0>;
};
};
port {
display_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
};
gpio-keys {
......@@ -122,3 +127,7 @@
};
};
};
&ipu_di0_disp0 {
remote-endpoint = <&display_in>;
};
......@@ -21,9 +21,8 @@
reg = <0x90000000 0x20000000>;
};
display@di0 {
display0: display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
......@@ -41,11 +40,16 @@
vsync-len = <10>;
};
};
port {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
};
display@di1 {
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
......@@ -68,6 +72,12 @@
pixelclk-active = <0>;
};
};
port {
display1_in: endpoint {
remote-endpoint = <&ipu_di1_disp1>;
};
};
};
gpio-keys {
......@@ -258,6 +268,14 @@
};
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&ipu_di1_disp1 {
remote-endpoint = <&display1_in>;
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
......
......@@ -79,6 +79,11 @@
};
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -92,13 +97,28 @@
};
ipu: ipu@40000000 {
#crtc-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp0: endpoint {
};
};
ipu_di1: port@3 {
reg = <3>;
ipu_di1_disp1: endpoint {
};
};