Commit c42b8fe9 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'regmap-fix-v4.6-rc7' of git://

Pull regmap fixes from Mark Brown:
 "This is rather too late so it'd be completely understandable if you
  don't want to pull it at this point, I had thought I'd sent this
  earlier but it seems I didn't.  Everything has been in -next for some
  time now.

  The main set of fixes here are mopping up some more issues with MMIO,
  fixing handling of endianness configuration in DT (which just wasn't
  working at all) and cases where the register and value endianness are

  There is also a fix for bulk register reads on SPMI"

* tag 'regmap-fix-v4.6-rc7' of git://
  regmap: spmi: Fix regmap_spmi_ext_read in multi-byte case
  regmap: mmio: Explicitly say little endian is the defualt in the bus config
  regmap: mmio: Parse endianness definitions from DT
  regmap: Fix implicit inclusion of device.h
  regmap: mmio: Fix value endianness selection
  regmap: fix documentation to match code
parents 90fa7c7f 2a2cd521
Device-Tree binding for regmap
The endianness mode of CPU & Device scenarios:
Index Device Endianness properties
1 BE 'big-endian'
2 LE 'little-endian'
3 Native 'native-endian'
For one device driver, which will run in different scenarios above
on different SoCs using the devicetree, we need one way to simplify
Devicetree binding for regmap
Optional properties:
- {big,little,native}-endian: these are boolean properties, if absent
then the implementation will choose a default based on the device
being controlled. These properties are for register values and all
the buffers only. Native endian means that the CPU and device have
the same endianness.
Scenario 1 : CPU in LE mode & device in LE mode.
dev: dev@40031000 {
compatible = "name";
reg = <0x40031000 0x1000>;
native-endian: See common-properties.txt for a definition
Scenario 2 : CPU in LE mode & device in BE mode.
dev: dev@40031000 {
compatible = "name";
reg = <0x40031000 0x1000>;
Regmap defaults to little-endian register access on MMIO based
devices, this is by far the most common setting. On CPU
architectures that typically run big-endian operating systems
(e.g. PowerPC), registers can be defined as big-endian and must
be marked that way in the devicetree.
Scenario 3 : CPU in BE mode & device in BE mode.
dev: dev@40031000 {
compatible = "name";
reg = <0x40031000 0x1000>;
On SoCs that can be operated in both big-endian and little-endian
modes, with a single hardware switch controlling both the endianess
of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
chips), "native-endian" is used to allow using the same device tree
blob in both cases.
Scenario 4 : CPU in BE mode & device in LE mode.
Scenario 1 : a register set in big-endian mode.
dev: dev@40031000 {
compatible = "name";
compatible = "syscon";
reg = <0x40031000 0x1000>;
......@@ -13,6 +13,7 @@
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/fs.h>
#include <linux/list.h>
......@@ -23,6 +23,8 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include "internal.h"
struct regmap_mmio_context {
void __iomem *regs;
unsigned val_bytes;
......@@ -212,6 +214,7 @@ static const struct regmap_bus regmap_mmio = {
.reg_write = regmap_mmio_write,
.reg_read = regmap_mmio_read,
.free_context = regmap_mmio_free_context,
.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
......@@ -245,7 +248,7 @@ static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
ctx->val_bytes = config->val_bits / 8;
ctx->clk = ERR_PTR(-ENODEV);
switch (config->reg_format_endian) {
switch (regmap_get_val_endian(dev, &regmap_mmio, config)) {
......@@ -142,7 +142,7 @@ static int regmap_spmi_ext_read(void *context,
while (val_size) {
len = min_t(size_t, val_size, 8);
err = spmi_ext_register_readl(context, addr, val, val_size);
err = spmi_ext_register_readl(context, addr, val, len);
if (err)
goto err_out;
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