1. 04 Sep, 2017 26 commits
  2. 01 Sep, 2017 1 commit
  3. 30 Aug, 2017 3 commits
    • Paul Burton's avatar
      clocksource: mips-gic-timer: Use new GIC accessor functions · e07127a0
      Paul Burton authored
      Switch from calling functions exported by the GIC interrupt controller
      to using new accessors provided by asm/mips-gic.h. This will allow the
      counter-handling functionality to be removed from the interrupt
      controller driver, where it doesn't really belong, and also allow for
      inlining of the accesses to the GIC.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17021/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    • Paul Burton's avatar
      MIPS: GIC: Introduce asm/mips-gic.h with accessor functions · 582e2b4a
      Paul Burton authored
      This patch introduces a new header providing accessor functions for the
      MIPS Global Interrupt Controller (GIC) mirroring those provided for the
      other 2 components of the MIPS Coherent Processing System (CPS) - the
      Coherence Manager (CM) & Cluster Power Controller (CPC).
      This header makes use of the new standardised CPS accessor macros where
      possible, but does require some custom accessors for cases where we have
      either a bit or a register per interrupt.
      A major advantage of this over the existing
      include/linux/irqchip/mips-gic.h definitions is that code performing
      accesses can become much simpler, for example this:
        gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
                        GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
                        (unsigned long)trig << GIC_INTR_BIT(intr));
      ...can become simply:
        change_gic_trig(intr, trig);
      The accessors handle 32 vs 64 bit in the same way as for CM & CPC code,
      which means that GIC code will also not need to worry about the access
      size in most cases. They are also accessible outside of
      drivers/irqchip/irq-mips-gic.c which will allow for simplification in
      the use of the non-interrupt portions of the GIC (eg. counters) which
      currently require the interrupt controller driver to expose helper
      functions for access.
      This patch doesn't change any existing code over to use the new
      accessors yet, since a wholesale change would be invasive & difficult to
      review. Instead follow-on patches will convert code piecemeal to use
      this new header. The one change to existing code is to rename gic_base
      to mips_gic_base & make it global, in order to fit in with the naming
      expected by the standardised CPS accessor macros.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17020/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    • James Hogan's avatar
      irqchip: mips-gic: SYNC after enabling GIC region · a0ffec3d
      James Hogan authored
      A SYNC is required between enabling the GIC region and actually trying
      to use it, even if the first access is a read, otherwise its possible
      depending on the timing (and in my case depending on the precise
      alignment of certain kernel code) to hit CM bus errors on that first
      Add the SYNC straight after setting the GIC base.
        Changes later in this series increase our likelihood of hitting this
        by reducing the amount of code that runs between enabling the GIC &
        accessing it.]
      Fixes: a7057270 ("irqchip: mips-gic: Add device-tree support")
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17019/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
  4. 29 Aug, 2017 10 commits