1. 10 Nov, 2017 1 commit
  2. 04 Apr, 2017 1 commit
  3. 30 Jan, 2017 1 commit
  4. 21 Sep, 2016 1 commit
    • Marek Vasut's avatar
      net: can: ifi: Configure transmitter delay · 8d58790b
      Marek Vasut authored
      
      
      Configure the transmitter delay register at +0x1c to correctly handle
      the CAN FD bitrate switch (BRS). This moves the SSP (secondary sample
      point) to a proper offset, so that the TDC mechanism works and won't
      generate error frames on the CAN link.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Marc Kleine-Budde <mkl@pengutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Oliver Hartkopp <socketcan@hartkopp.net>
      Cc: Wolfgang Grandegger <wg@grandegger.com>
      Cc: linux-stable <stable@vger.kernel.org>
      Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      8d58790b
  5. 09 May, 2016 6 commits
  6. 10 Mar, 2016 4 commits
    • Marek Vasut's avatar
      can: ifi: Add obscure bit swap for EFF frame IDs · 6cc64266
      Marek Vasut authored
      
      
      In case of CAN2.0 EFF frame, the controller handles frame IDs in a
      rather bizzare way. The ID is split into an extended part, IDX[28:11]
      and standard part, ID[10:0]. In the TX path, the core first sends the
      top 11 bits of the IDX, followed by ID and finally the rest of IDX.
      In the RX path, the core stores the ID the LSbit part of IDX field,
      followed by the LSbit parts of real IDX. The MSbit parts of IDX are
      stored in ID field of the register.
      
      This patch implements the necessary bit shuffling to mitigate this
      obscure behavior. In case two of these controllers are connected
      together, the RX and TX bit swapping nullifies itself and the issue
      does not manifest. The issue only manifests when talking to another
      different CAN controller.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Marc Kleine-Budde <mkl@pengutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Oliver Hartkopp <socketcan@hartkopp.net>
      Cc: Wolfgang Grandegger <wg@grandegger.com>
      Reviewed-by: default avatarOliver Hartkopp <socketcan@hartkopp.net>
      Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      6cc64266
    • Marek Vasut's avatar
      can: ifi: Fix RX and TX ID mask · 22365435
      Marek Vasut authored
      
      
      The RX and TX ID mask for CAN2.0 is 11 bits wide. This patch fixes
      the incorrect mask, which caused the CAN IDs to miss the MSBit both
      on receive and transmit.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Marc Kleine-Budde <mkl@pengutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Oliver Hartkopp <socketcan@hartkopp.net>
      Cc: Wolfgang Grandegger <wg@grandegger.com>
      Reviewed-by: default avatarOliver Hartkopp <socketcan@hartkopp.net>
      Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      22365435
    • Marek Vasut's avatar
      can: ifi: Fix TX DLC configuration · f1deaee0
      Marek Vasut authored
      
      
      The TX DLC, the transmission length information, was not written
      into the transmit configuration register. When using the CAN core
      with different CAN controller, the receiving CAN controller will
      receive only the ID part of the CAN frame, but no data at all.
      
      This patch adds the TX DLC into the register to fix this issue.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Marc Kleine-Budde <mkl@pengutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Oliver Hartkopp <socketcan@hartkopp.net>
      Cc: Wolfgang Grandegger <wg@grandegger.com>
      Reviewed-by: default avatarOliver Hartkopp <socketcan@hartkopp.net>
      Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      f1deaee0
    • Marek Vasut's avatar
      can: ifi: Fix clock generator configuration · 99312c37
      Marek Vasut authored
      
      
      The clock generation does not match reality when using the CAN IP
      core outside of the FPGA design. This patch fixes the computation
      of values which are programmed into the clock generator registers.
      
      First, there are some off-by-one errors which manifest themselves
      only when communicating with different controller, so those are
      fixed.
      
      Second, the bits in the clock generator registers have different
      meaning depending on whether the core is in ISO CANFD mode or any
      of the other modes (BOSCH CANFD or CAN2.0). Detect the ISO CANFD
      mode and fix handling of this special case of clock configuration.
      
      Finally, the CAN clock speed is in CANCLOCK register, not SYSCLOCK
      register, so fix this as well.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Marc Kleine-Budde <mkl@pengutronix.de>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Oliver Hartkopp <socketcan@hartkopp.net>
      Cc: Wolfgang Grandegger <wg@grandegger.com>
      Reviewed-by: default avatarOliver Hartkopp <socketcan@hartkopp.net>
      Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
      99312c37
  7. 20 Feb, 2016 1 commit