Gustavo Padovan authored Aug 29, 2016 and Robert Foss committed Oct 25, 2018

Following the support for fences on the virtio driver add support
for native fence on virgl. This was somewhat based on the freedeno one.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Signed-off-by: Robert Foss <robert.foss@collabora.com>

u_transfer_helper already had code to handle treating packed Z32_S8
as separate Z32_FLOAT and S8_UINT resources, since some drivers can't
handle that interleaved format natively.

Other hardware needs depth and stencil as separate resources for all
formats.  For example, V3D3 needs this for 24-bit depth as well.

This patch adds a new flag to lower all depth/stencils formats, and
implements support for Z24_UNORM_S8_UINT.  (S8_UINT_Z24_UNORM is left
as an exercise to the reader, preferably someone who has access to a
machine that uses that format.)

Reviewed-by: Eric Anholt <eric@anholt.net>

This new function takes separate Z24 depth and S8 stencil sources,
and packs them into a single combined Z24S8 buffer.

Reviewed-by: Eric Anholt <eric@anholt.net>

This will be used by u_transfer_helper.c shortly, in order to split
packed depth-stencil into separate resources.

Reviewed-by: Eric Anholt <eric@anholt.net>

This is needed for nir_gather_info to actually count the textures,
since it operates solely on variables.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>

This is needed for nir_gather_info to actually count the new textures,
since it operates solely on variables.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>

This corresponds to commit 801cca8104245c07e8cc532 on GitHub.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

sb/sb_bc_parser.cpp:620:27: warning: use of logical '&&' with constant operand [-Wconstant-logical-operand]
        if (cf->bc.op_ptr->flags && FF_GDS)
                                 ^  ~~~~~~
sb/sb_bc_parser.cpp:620:27: note: use '&' for a bitwise operation
        if (cf->bc.op_ptr->flags && FF_GDS)
                                 ^~
                                 &
sb/sb_bc_parser.cpp:620:27: note: remove constant to silence this warning
        if (cf->bc.op_ptr->flags && FF_GDS)
                                ~^~~~~~~~~

Fixes: da977ad9 ("r600/sb: start adding GDS support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the
right thing and use the enum.

v2: fix intel_miptree_finish_depth too (Caio)

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113


Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

SCons MSVC support relies on vcvarsall.bat to extract the PATH, CPP
includes, library paths, etc.

And SCons also has an build env var named MSVC_USE_SCRIPT which one can
use to point to alternative vcvarsall.bat script.

This change exposes this MSVC_USE_SCRIPT build env variable as a SCons
command line variable.  This will enable using MSVC outside Program
Files (e.g, network shares, etc.)

This change also links advapi32 library, necessary for the Windows
Registry API used by WGL state tracker, avoiding missing symbols.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

This fixes some new memory model tests:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.*

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108112


Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

v2: - change how the access qualifiers are accumulated
v3: - duplicate members in struct_member_decoration_cb()
    - handle access qualifiers on variables
    - remove access qualifiers handling in _vtn_variable_load_store()
    - fix setting access qualifiers on type->array_element

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Fixes: e4538b93 "anv: Implement VK_KHR_driver_properties"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>

This is basically a port of commit,
3ade7666
("i965: Disable 3DSTATE_WM_HZ_OP fields.")

The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in
the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
Clear." It mentions that the packet overrides GPU state for the clear
operation and needs to be reset to 0s to clear the overrides. Depending
on the kernel, we may not get a context with the GPU state for this
packet zeroed. Do it ourselves just in case.

Prevents a number of GPU hangs when running crucible on ICL. I tried to
get the exact number of hangs that occurs without this patch, but was
unsuccessful. The test machine became unresponsive before completing the
full run.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Ref: 263b584d "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake."
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

Ref: 263b584d "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake."
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

The b2f and b2i conversions always produce zero or one which are both
representable in every type and size.  Since b2i and b2f support all bit
sizes, we can just get rid of the conversion opcode.

total instructions in shared programs: 15089335 -> 15084368 (-0.03%)
instructions in affected programs: 212564 -> 207597 (-2.34%)
helped: 896
HURT: 0

total cycles in shared programs: 369831123 -> 369826267 (<.01%)
cycles in affected programs: 2008647 -> 2003791 (-0.24%)
helped: 693
HURT: 216

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

This is valid NIR but you can't actually hit this case today.  GLSL IR
doesn't have a bool to double opcode; it does f2d(b2f(x)).  In SPIR-V we
don't have any to/from bool conversion opcodes at all.  However, the
next commit will make us start generating it so we should be ready.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Several of the Atom GPUs have additional restrictions on alignment when
moving < 64-bit source to a 64-bit destination.  All of the nir_op_*2*64
code generation paths respected this, but nir_op_b2[fi] did not.

Previous to commit a68dd47b it was not possible to generate such an
instruction from the GLSL path.  It may have been possible from SPIR-V,
but it's not clear.  The aforementioned patch converts a 64-bit
nir_op_fsign into a sequence of operations including a nir_op_b2f with a
64-bit result.  This "just works" everywhere except these Atom parts.

This problem was not detected during normal CI testing because the Atom
parts are not included in developer builds.

v2 (idr): Make the patch compile, and make some cosmetic changes.  Add a
commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319


Fixes: a68dd47b "nir/algebraic: Simplify fsat of fsign"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

Fixed pack_uint_Z_FLOAT32 by casting row data to float instead uint.
Remove code duplicate function pack_uint_Z_FLOAT32_X24S8.
Edited case in "_mesa_get_pack_uint_z_func".
Now it looks like "_mesa_get_pack_float_z_func".
Remove _mesa_problem call, which was added for debuging this issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91433


Signed-off-by: Illia Iorin <illia.iorin@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.

This follows the ids and approach used on kernel's commit
b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
and commit c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")

v2: Lionel noticed that GT{1,2,3} on kernel wasn't following
spec when looking to number of EUs, so kernel has been updated.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.

v2: add input size check, return error when size out of bounds
v3: fix the size check for vaimage
v4: add size adjustment for x and y coordinates

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Christian König <christian.koenig@amd.com>

This fixes crashes for some CTS:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_*

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113


Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

R32G32B32 are weird formats and we are only going to support
some basic operations for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Otherwise, Yakuza and The Evil Within hang the GPU with DXVK.
This apparently only works on Polaris.

Suggested by Marek.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

The es check is already covered by the is_version() check.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Found by coverity

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Found by coverity

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

The value is always >= 0 here.

Found by coverity

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

We have never opened master_Fd at this point, so remove code to
close it.

Found by coverity.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Coverity pointed out we were copying 168 bytes here unnecessarily.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Not going to matter, but be consistent.

Found by coverity

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: caf41c78 (anv/allocator: Support softpin in the BO cache)

This fixes a bug uncovered by my NIR integer division by constant
optimization series.

Fixes: 19f9cb72 "i965/fs: Add pass to propagate conditional..."
Fixes: 627f94b7 "i965/vec4: adding vec4_cmod_propagation..."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

While I generally trust rediculousfish to have done his homework, we've
made some adjustments to suit the needs of mesa and it'd be good to
test those.  Also, there's no better place than unit tests to clearly
document the different edge cases of the different methods.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

There's nothing inherently fixed-width in the code.  All that's required
to generalize it is to make everything internally 64-bit and pass
UINT_BITS in as a parameter to util_compute_fast_[us]div_info.  With
that, it can now handle 8, 16, 32, and 64-bit integer division by a
constant.

We also add support for division by 1 and by other powers of 2.  This is
useful if you want to divide by a uniform value in a shader where you
have the opportunity to adjust the uniform on the CPU before passing it
in.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>