mt7628a.dtsi 6.75 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0
2
#include <dt-bindings/clock/mt7628-clk.h>
3
#include <dt-bindings/reset/mt7628-reset.h>
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "ralink,mt7628a-soc";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "mti,mips24KEc";
			device_type = "cpu";
			reg = <0>;
		};
	};

	cpuintc: interrupt-controller {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		compatible = "mti,cpu-interrupt-controller";
	};

	palmbus@10000000 {
		compatible = "palmbus", "simple-bus";
		reg = <0x10000000 0x200000>;
		ranges = <0x0 0x10000000 0x1FFFFF>;

		#address-cells = <1>;
		#size-cells = <1>;

		sysc: system-controller@0 {
			compatible = "ralink,mt7620a-sysc", "syscon";
			reg = <0x0 0x100>;
		};

41
42
43
44
45
46
47
		syscon-reboot {
			compatible = "syscon-reboot";
			regmap = <&sysc>;
			offset = <0x34>;
			mask = <0x1>;
		};

48
49
50
51
52
53
54
55
		clkctrl: clkctrl@0x2c {
			reg = <0x2c 0x8>, <0x10 0x4>;
			reg-names = "syscfg0", "clkcfg";
			compatible = "mediatek,mt7628-clk";
			#clock-cells = <1>;
			u-boot,dm-pre-reloc;
		};

56
57
58
59
60
61
		rstctrl: rstctrl@0x34 {
			reg = <0x34 0x4>;
			compatible = "mediatek,mtmips-reset";
			#reset-cells = <1>;
		};

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
		pinctrl: pinctrl@60 {
			compatible = "mediatek,mt7628-pinctrl";
			reg = <0x3c 0x2c>, <0x1300 0x100>;
			reg-names = "gpiomode", "padconf";

			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pin_state {
			};

			spi_single_pins: spi_single_pins {
				groups = "spi";
				function = "spi";
			};

			spi_dual_pins: spi_dual_pins {
				spi_master_pins {
					groups = "spi";
					function = "spi";
				};

				spi_cs1_pin {
					groups = "spi cs1";
					function = "spi cs1";
				};
			};

			uart0_pins: uart0_pins {
				groups = "uart0";
				function = "uart0";
			};

			uart1_pins: uart1_pins {
				groups = "uart1";
				function = "uart1";
			};

			uart2_pins: uart2_pins {
				groups = "uart2";
				function = "uart2";
			};

			i2c_pins: i2c_pins {
				groups = "i2c";
				function = "i2c";
			};

			ephy_iot_mode: ephy_iot_mode {
				ephy4_1_dis {
					groups = "ephy4_1_pad";
					function = "digital";
				};

				ephy0_en {
					groups = "ephy0";
					function = "enable";
				};
			};

			ephy_router_mode: ephy_router_mode {
				ephy4_1_en {
					groups = "ephy4_1_pad";
					function = "analog";
				};

				ephy0_en {
					groups = "ephy0";
					function = "enable";
				};
			};

			sd_iot_mode: sd_iot_mode {
				ephy4_1_dis {
					groups = "ephy4_1_pad";
					function = "digital";
				};

				sdxc_en {
					groups = "sdmode";
					function = "sdxc";
				};

				sdxc_iot_mode {
					groups = "sd router";
					function = "iot";
				};

				sd_clk_pad {
					pins = "sd_clk";
					drive-strength-4g = <8>;
				};
			};

			sd_router_mode: sd_router_mode {
				sdxc_router_mode {
					groups = "sd router";
					function = "router";
				};

				sdxc_map_pins {
					groups = "gpio0", "i2s", "sdmode", \
						 "i2c", "uart1";
					function = "gpio";
				};

				sd_clk_pad {
					pins = "gpio0";
					drive-strength-28 = <8>;
				};
			};

			emmc_iot_8bit_mode: emmc_iot_8bit_mode {
				ephy4_1_dis {
					groups = "ephy4_1_pad";
					function = "digital";
				};

				emmc_en {
					groups = "sdmode";
					function = "sdxc";
				};

				emmc_iot_mode {
					groups = "sd router";
					function = "iot";
				};

				emmc_d4_d5 {
					groups = "uart2";
					function = "sdxc d5 d4";
				};

				emmc_d6 {
					groups = "pwm1";
					function = "sdxc d6";
				};

				emmc_d7 {
					groups = "pwm0";
					function = "sdxc d7";
				};

				sd_clk_pad {
					pins = "sd_clk";
					drive-strength-4g = <8>;
				};
			};
		};

212
213
214
215
		watchdog: watchdog@100 {
			compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
			reg = <0x100 0x30>;

216
			resets = <&rstctrl MT7628_TIMER_RST>;
217
218
219
220
221
222
			reset-names = "wdt";

			interrupt-parent = <&intc>;
			interrupts = <24>;
		};

223
224
225
226
227
228
229
		intc: interrupt-controller@200 {
			compatible = "ralink,rt2880-intc";
			reg = <0x200 0x100>;

			interrupt-controller;
			#interrupt-cells = <1>;

230
			resets = <&rstctrl MT7628_INT_RST>;
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
			reset-names = "intc";

			interrupt-parent = <&cpuintc>;
			interrupts = <2>;

			ralink,intc-registers = <0x9c 0xa0
						 0x6c 0xa4
						 0x80 0x78>;
		};

		memory-controller@300 {
			compatible = "ralink,mt7620a-memc";
			reg = <0x300 0x100>;
		};

246
247
248
249
250
251
252
		gpio@600 {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
			reg = <0x600 0x100>;

253
254
255
			resets = <&rstctrl MT7628_PIO_RST>;
			reset-names = "pio";

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
			interrupt-parent = <&intc>;
			interrupts = <6>;

			gpio0: bank@0 {
				reg = <0>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio1: bank@1 {
				reg = <1>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio2: bank@2 {
				reg = <2>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
				#gpio-cells = <2>;
			};
		};

281
282
283
		spi0: spi@b00 {
			compatible = "ralink,mt7621-spi";
			reg = <0xb00 0x40>;
284
285
286
287

			resets = <&rstctrl MT7628_SPI_RST>;
			reset-names = "spi";

288
289
			#address-cells = <1>;
			#size-cells = <0>;
290

291
			clocks = <&clkctrl CLK_SPI>;
292
293
294
		};

		uart0: uartlite@c00 {
295
			compatible = "mediatek,hsuart", "ns16550a";
296
297
			reg = <0xc00 0x100>;

298
299
300
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;

301
			clocks = <&clkctrl CLK_UART0>;
302

303
			resets = <&rstctrl MT7628_UART0_RST>;
304
305
306
307
308
309
310
311
312
			reset-names = "uart0";

			interrupt-parent = <&intc>;
			interrupts = <20>;

			reg-shift = <2>;
		};

		uart1: uart1@d00 {
313
			compatible = "mediatek,hsuart", "ns16550a";
314
315
			reg = <0xd00 0x100>;

316
317
318
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pins>;

319
			clocks = <&clkctrl CLK_UART1>;
320

321
			resets = <&rstctrl MT7628_UART1_RST>;
322
323
324
325
326
327
328
329
330
			reset-names = "uart1";

			interrupt-parent = <&intc>;
			interrupts = <21>;

			reg-shift = <2>;
		};

		uart2: uart2@e00 {
331
			compatible = "mediatek,hsuart", "ns16550a";
332
333
			reg = <0xe00 0x100>;

334
335
336
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pins>;

337
			clocks = <&clkctrl CLK_UART2>;
338

339
			resets = <&rstctrl MT7628_UART2_RST>;
340
341
342
343
344
345
346
347
348
			reset-names = "uart2";

			interrupt-parent = <&intc>;
			interrupts = <22>;

			reg-shift = <2>;
		};
	};

349
	eth@10110000 {
350
		compatible = "mediatek,mt7628-eth";
351
352
353
		reg = <0x10100000 0x10000
		       0x10110000 0x8000>;

354
355
356
		resets = <&rstctrl MT7628_EPHY_RST>;
		reset-names = "ephy";

357
358
359
		syscon = <&sysc>;
	};

360
361
362
363
364
365
366
	usb_phy: usb-phy@10120000 {
		compatible = "mediatek,mt7628-usbphy";
		reg = <0x10120000 0x1000>;

		#phy-cells = <0>;

		ralink,sysctl = <&sysc>;
367

368
369
		resets = <&rstctrl MT7628_UPHY_RST>;
		reset-names = "phy";
370
371
372

		clocks = <&clkctrl CLK_UPHY>;
		clock-names = "cg";
373
374
375
376
377
378
379
380
381
382
383
384
385
	};

	ehci@101c0000 {
		compatible = "generic-ehci";
		reg = <0x101c0000 0x1000>;

		phys = <&usb_phy>;
		phy-names = "usb";

		interrupt-parent = <&intc>;
		interrupts = <18>;
	};
};