Commit 15147dc6 authored by Tom Rini's avatar Tom Rini

Merge branch '2019-10-24-ti-imports'

- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
parents 271103ac d0e134b9
......@@ -32,3 +32,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};
......@@ -44,3 +44,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};
......@@ -44,3 +44,20 @@
&mmc2_iodelay_hs200_rev20_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};
......@@ -24,3 +24,20 @@
&mmc2_iodelay_hs200_conf {
u-boot,dm-spl;
};
&omap_dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
dr_mode = "peripheral";
};
&usb2_phy1 {
u-boot,dm-spl;
};
&usb3_phy1 {
u-boot,dm-spl;
};
......@@ -74,6 +74,8 @@
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
......@@ -86,6 +88,8 @@
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by the AM65x_DRA80xM EMIF Tool:
* This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
* http://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600
* Data Rate: 1600 MT/s
* ECC Enabled: No
* Data Width: 32
* Data Width: 32 bits
*/
#define DDR_PLL_FREQUENCY 400000000
#define DDRSS_V2H_CTL_REG 0x000073FF
#define DDRCTL_MSTR 0x41040010
#define DDRCTL_RFSHCTL0 0x00210070
#define DDRCTL_ECCCFG0 0x00000000
......@@ -32,10 +33,10 @@
#define DDRCTL_DRAMTMG5 0x04040302
#define DDRCTL_DRAMTMG6 0x00000004
#define DDRCTL_DRAMTMG7 0x00000404
#define DDRCTL_DRAMTMG8 0x03030C05
#define DDRCTL_DRAMTMG8 0x03030A05
#define DDRCTL_DRAMTMG9 0x00020208
#define DDRCTL_DRAMTMG10 0x001C180A
#define DDRCTL_DRAMTMG11 0x1106010E
#define DDRCTL_DRAMTMG11 0x0E06010E
#define DDRCTL_DRAMTMG12 0x00020008
#define DDRCTL_DRAMTMG13 0x0B100002
#define DDRCTL_DRAMTMG14 0x00000000
......@@ -47,7 +48,7 @@
#define DDRCTL_DFITMG1 0x000A0606
#define DDRCTL_DFITMG2 0x00000604
#define DDRCTL_DFIMISC 0x00000001
#define DDRCTL_ADDRMAP0 0x001F1F1F
#define DDRCTL_ADDRMAP0 0x0000001F
#define DDRCTL_ADDRMAP1 0x003F0808
#define DDRCTL_ADDRMAP2 0x00000000
#define DDRCTL_ADDRMAP3 0x00000000
......@@ -83,13 +84,13 @@
#define DDRPHY_DCR 0x0000040C
#define DDRPHY_DTPR0 0x041A0B06
#define DDRPHY_DTPR1 0x28140000
#define DDRPHY_DTPR2 0x0034E300
#define DDRPHY_DTPR3 0x02800800
#define DDRPHY_DTPR2 0x0034E255
#define DDRPHY_DTPR3 0x01D50800
#define DDRPHY_DTPR4 0x31180805
#define DDRPHY_DTPR5 0x00250B06
#define DDRPHY_DTPR6 0x00000505
#define DDRPHY_ZQCR 0x008A2A58
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x000077DD
#define DDRPHY_MR0 0x00000214
#define DDRPHY_MR1 0x00000501
......@@ -109,6 +110,8 @@
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
#define DDRPHY_DTCR0 0x8000B1C7
#define DDRPHY_DTCR1 0x00010236
#define DDRPHY_ACIOCR0 0x30070000
#define DDRPHY_ACIOCR3 0x00000001
#define DDRPHY_ACIOCR5 0x04800000
#define DDRPHY_IOVCR0 0x0F0C0C0C
#define DDRPHY_DX0GCR0 0x00000000
......@@ -148,9 +151,12 @@
#define DDRPHY_DX3GTR0 0x00020002
#define DDRPHY_DX4GTR0 0x00020002
#define DDRPHY_ODTCR 0x00010000
#define DDRPHY_DX8SL0IOCR 0x04800000
#define DDRPHY_DX8SL1IOCR 0x04800000
#define DDRPHY_DX8SL2IOCR 0x04800000
#define DDRPHY_DX8SL0IOCR 0x74800000
#define DDRPHY_DX8SL1IOCR 0x74800000
#define DDRPHY_DX8SL2IOCR 0x74800000
#define DDRPHY_DX8SL0DXCTL2 0x00141830
#define DDRPHY_DX8SL1DXCTL2 0x00141830
#define DDRPHY_DX8SL2DXCTL2 0x00141830
#define DDRPHY_DX8SL0DQSCTL 0x01264000
#define DDRPHY_DX8SL1DQSCTL 0x01264000
#define DDRPHY_DX8SL2DQSCTL 0x01264000
......@@ -17,6 +17,10 @@
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;
ti,ss-reg = <
DDRSS_V2H_CTL_REG
>;
ti,ctl-reg = <
DDRCTL_DFIMISC
DDRCTL_DFITMG0
......@@ -132,12 +136,15 @@
DDRPHY_DX8SL0DXCTL2
DDRPHY_DX8SL0IOCR
DDRPHY_DX8SL0PLLCR0
DDRPHY_DX8SL0DQSCTL
DDRPHY_DX8SL1DXCTL2
DDRPHY_DX8SL1IOCR
DDRPHY_DX8SL1PLLCR0
DDRPHY_DX8SL1DQSCTL
DDRPHY_DX8SL2DXCTL2
DDRPHY_DX8SL2IOCR
DDRPHY_DX8SL2PLLCR0
DDRPHY_DX8SL2DQSCTL
DDRPHY_DXCCR
DDRPHY_ODTCR
DDRPHY_PGCR0
......@@ -168,6 +175,8 @@
>;
ti,phy-ioctl = <
DDRPHY_ACIOCR0
DDRPHY_ACIOCR3
DDRPHY_ACIOCR5
DDRPHY_IOVCR0
>;
......
......@@ -7,7 +7,7 @@
#include "k3-am654.dtsi"
#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
/ {
......
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......@@ -6,6 +6,8 @@
/dts-v1/;
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-3733.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
aliases {
......
......@@ -22,6 +22,7 @@
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp", "simple-bus";
u-boot,dm-spl;
};
ocp2scp@4a090000 {
......
......@@ -224,6 +224,8 @@ static void do_nonsec_virt_switch(void)
}
#endif
__weak void board_prep_linux(bootm_headers_t *images) { }
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
......@@ -270,6 +272,8 @@ static void boot_prep_linux(bootm_headers_t *images)
printf("FDT and ATAGS support not compiled in - hanging\n");
hang();
}
board_prep_linux(images);
}
__weak bool armv7_boot_nonsec_default(void)
......
......@@ -233,3 +233,14 @@ int print_cpuinfo(void)
return 0;
}
#endif
#ifdef CONFIG_ARM64
void board_prep_linux(bootm_headers_t *images)
{
debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
images->os.start, images->os.end);
__asm_flush_dcache_range(images->os.start,
ROUND(images->os.end,
CONFIG_SYS_CACHELINE_SIZE));
}
#endif
......@@ -73,7 +73,7 @@ static void store_boot_index_from_rom(void)
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
#if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
struct udevice *dev;
int ret;
#endif
......@@ -117,6 +117,12 @@ void board_init_f(ulong dummy)
/* Prepare console output */
preloader_console_init();
#endif
#if defined(CONFIG_K3_J721E_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
}
u32 spl_boot_mode(const u32 boot_device)
......
......@@ -21,6 +21,7 @@ config TARGET_J721E_R5_EVM
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_J721E_DDRSS
imply SYS_K3_SPL_ATF
endchoice
......
......@@ -48,6 +48,9 @@ static int booti_start(cmd_tbl_t *cmdtp, int flag, int argc,
}
images->ep = relocated_addr;
images->os.start = relocated_addr;
images->os.end = relocated_addr + image_size;
lmb_reserve(&images->lmb, images->ep, le32_to_cpu(image_size));
/*
......
......@@ -25,8 +25,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_CMD_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
......@@ -39,7 +42,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
......@@ -85,6 +88,7 @@ CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPL_PHY=y
CONFIG_PIPE3_PHY=y
CONFIG_SPL_PIPE3_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
......@@ -107,7 +111,9 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
......
......@@ -30,8 +30,11 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_MTDPARTS=y
......@@ -42,7 +45,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000
CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0xA000
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_MMC=y
......@@ -88,6 +91,7 @@ CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPL_PHY=y
CONFIG_PIPE3_PHY=y
CONFIG_SPL_PIPE3_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_PMIC_PALMAS=y
CONFIG_PMIC_LP873X=y
......@@ -110,7 +114,9 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
......
This diff is collapsed.
......@@ -54,5 +54,16 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
depends on RAM
help
The J721E DDR subsystem comprises DDR controller, DDR PHY and
wrapper logic to integrate these blocks in the device. The DDR
subsystem is used to provide an interface to external SDRAM
devices which can be utilized for storing program or data.
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
......@@ -14,3 +14,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
This diff is collapsed.
......@@ -996,6 +996,10 @@
PGSR0_DIDONE_MASK)
#define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK)
struct ddrss_ss_reg_params {
u32 ddrss_v2h_ctl_reg;
};
struct ddrss_ddrctl_reg_params {
u32 ddrctl_dfimisc;
u32 ddrctl_dfitmg0;
......@@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params {
u32 ddrphy_dx8sl0dxctl2;
u32 ddrphy_dx8sl0iocr;
u32 ddrphy_dx8sl0pllcr0;
u32 ddrphy_dx8sl0dqsctl;
u32 ddrphy_dx8sl1dxctl2;
u32 ddrphy_dx8sl1iocr;
u32 ddrphy_dx8sl1pllcr0;
u32 ddrphy_dx8sl1dqsctl;
u32 ddrphy_dx8sl2dxctl2;
u32 ddrphy_dx8sl2iocr;
u32 ddrphy_dx8sl2pllcr0;
u32 ddrphy_dx8sl2dqsctl;
u32 ddrphy_dxccr;
u32 ddrphy_odtcr;
u32 ddrphy_pgcr0;
......@@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params {
};
struct ddrss_ddrphy_ioctl_params {
u32 ddrphy_aciocr0;
u32 ddrphy_aciocr3;
u32 ddrphy_aciocr5;
u32 ddrphy_iovcr0;
};
......@@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params {
};
struct ddrss_params {
struct ddrss_ss_reg_params ss_reg;
struct ddrss_ddrctl_reg_params ctl_reg;
struct ddrss_ddrctl_crc_params ctl_crc;
struct ddrss_ddrctl_ecc_params ctl_ecc;
......
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
#
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
/* SPDX-License-Identifier: BSD-3-Clause */
/******************************************************************************
*
* Copyright (C) 2017-2018 Cadence Design Systems, Inc.
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*
* cps_drv_lpddr4.h
* Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
*****************************************************************************
*/
#ifndef CPS_DRV_H_
#define CPS_DRV_H_
#include <stddef.h>
#include <inttypes.h>
#include <asm/io.h>
/**
* \brief Read a 32-bit value from memory.
* \param reg address of the memory mapped hardware register
* \return the value at the given address
*/
#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
/**
* \brief Write a 32-bit address value to memory.
* \param reg address of the memory mapped hardware register
* \param value unsigned 32-bit value to write
*/
#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
/**
* \brief Subtitue the value of fld macro and concatinate with required string
* \param fld field name
*/
#define CPS_FLD_MASK(fld) (fld ## _MASK)
#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
/**
* \brief Read a value of bit-field from the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \return bit-field value
*/
#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_SHIFT(fld)), \
(uint32_t)(reg_value)))
/**
* \brief Write a value of the bit-field into the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \param value value to be written to bit-field
* \return modified register value
*/
#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_SHIFT(fld)), \
(uint32_t)(reg_value), (uint32_t)(value)))
/**
* \brief Set bit within the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \return modified register value
*/
#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
(uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_WOCLR(fld)), \
(uint32_t)(reg_value)))
static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
{
uint32_t result = (reg_value & mask) >> shift;
return (result);
}
/**
* \brief Write a value of the bit-field into the register value.
* \param mask mask for the bit-field
* \param shift bit-field shift from LSB
* \param reg_value register value
* \param value value to be written to bit-field
* \return modified register value
*/
static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
{
uint32_t new_value = (value << shift) & mask;
new_value = (reg_value & ~mask) | new_value;
return (new_value);
}
/**
* \brief Set bit within the register value.
* \param width width of the bit-field
* \param mask mask for the bit-field
* \param is_woclr is bit-field has 'write one to clear' flag set
* \param reg_value register value
* \return modified register value
*/
static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
{
uint32_t new_value = reg_value;
/* Confirm the field to be bit and not write to clear type */
if ((width == 1U) && (is_woclr == 0U)) {
new_value |= mask;
}
return (new_value);
}
#endif /* CPS_DRV_H_ */
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