Commit ffc379b4 authored by Tom Rini's avatar Tom Rini

Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
parents 15147dc6 ec54c8c0
......@@ -76,12 +76,18 @@ config ARCH_BMIPS
config ARCH_MTMIPS
bool "Support MediaTek MIPS platforms"
select CLK
imply CMD_DM
select DISPLAY_CPUINFO
select DM
imply DM_ETH
imply DM_GPIO
select DM_RESET
select DM_SERIAL
select PINCTRL
select PINMUX
select PINCONF
select RESET_MTMIPS
imply DM_SPI
imply DM_SPI_FLASH
select LAST_STAGE_INIT
......@@ -408,9 +414,17 @@ config SYS_ICACHE_LINE_SIZE
help
The size of L1 Icache lines, if known at compile time.
config SYS_SCACHE_LINE_SIZE
int
default 0
help
The size of L2 cache lines, if known at compile time.
config SYS_CACHE_SIZE_AUTO
def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
SYS_SCACHE_LINE_SIZE = 0
help
Select this (or let it be auto-selected by not defining any cache
sizes) in order to allow U-Boot to automatically detect the sizes
......
......@@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb
dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
dtb-$(CONFIG_BOARD_BROADCOM_BCM968380GERG) += brcm,bcm968380gerg.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5315U) += comtrend,ar-5315u.dtb
dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
......@@ -19,10 +20,9 @@ dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
dtb-$(CONFIG_SOC_BMIPS_BCM6358) += sfr,nb4-ser.dtb
dtb-$(CONFIG_SOC_BMIPS_BCM6838) += brcm,bcm968380gerg.dtb
dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
......
......@@ -141,6 +141,24 @@
status = "disabled";
};
nand: nand-controller@10000200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6368",
"brcm,brcmnand-v4.0",
"brcm,brcmnand";
reg-names = "nand",
"nand-cache",
"nand-int-base";
reg = <0x10000200 0x180>,
<0x10000600 0x200>,
<0x100000b0 0x10>;
clocks = <&periph_clk BCM63268_CLK_NAND>;
clock-names = "nand";
status = "disabled";
};
periph_pwr: power-controller@1000184c {
compatible = "brcm,bcm6328-power-domain";
reg = <0x1000184c 0x4>;
......
......@@ -124,6 +124,22 @@
status = "disabled";
};
nand: nand-controller@10000200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6368",
"brcm,brcmnand-v2.2",
"brcm,brcmnand";
reg-names = "nand",
"nand-cache",
"nand-int-base";
reg = <0x10000200 0x180>,
<0x10000400 0x200>,
<0x100000b0 0x10>;
status = "disabled";
};
leds: led-controller@10000800 {
compatible = "brcm,bcm6328-leds";
reg = <0x10000800 0x24>;
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*/
#include <dt-bindings/clock/bcm6362-clock.h>
......@@ -135,6 +135,24 @@
status = "disabled";
};
nand: nand-controller@10000200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6368",
"brcm,brcmnand-v2.2",
"brcm,brcmnand";
reg-names = "nand",
"nand-cache",
"nand-int-base";
reg = <0x10000200 0x180>,
<0x10000600 0x200>,
<0x100000b0 0x10>;
clocks = <&periph_clk BCM6362_CLK_NAND>;
clock-names = "nand";
status = "disabled";
};
lsspi: spi@10000800 {
compatible = "brcm,bcm6358-spi";
reg = <0x10000800 0x70c>;
......
......@@ -146,6 +146,24 @@
status = "disabled";
};
nand: nand-controller@10000200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6368",
"brcm,brcmnand-v2.1",
"brcm,brcmnand";
reg-names = "nand",
"nand-cache",
"nand-int-base";
reg = <0x10000200 0x180>,
<0x10000600 0x200>,
<0x100000b0 0x10>;
clocks = <&periph_clk BCM6368_CLK_NAND>;
clock-names = "nand";
status = "disabled";
};
spi: spi@10000800 {
compatible = "brcm,bcm6358-spi";
reg = <0x10000800 0x70c>;
......
......@@ -99,6 +99,19 @@
};
};
&nand {
status = "okay";
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <15>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
brcm,nand-oob-sector-size = <64>;
};
};
&ohci {
status = "okay";
};
......
......@@ -85,15 +85,26 @@
};
};
&pinctrl {
state_default: pin_state {
p0led {
groups = "p0led_a";
function = "led";
};
};
};
&uart0 {
status = "okay";
clock-frequency = <40000000>;
};
&spi0 {
status = "okay";
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi_dual_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
......@@ -110,3 +121,9 @@
reg = <1>;
};
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&ephy_iot_mode>;
mediatek,poll-link-phy = <0>;
};
......@@ -26,9 +26,17 @@
};
};
&pinctrl {
state_default: pin_state {
p0led {
groups = "p0led_a";
function = "led";
};
};
};
&uart2 {
status = "okay";
clock-frequency = <40000000>;
};
&spi0 {
......@@ -43,3 +51,9 @@
reg = <0>;
};
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&ephy_iot_mode>;
mediatek,poll-link-phy = <0>;
};
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mt7628-clk.h>
#include <dt-bindings/reset/mt7628-reset.h>
/ {
#address-cells = <1>;
......@@ -16,11 +18,6 @@
};
};
resetc: reset-controller {
compatible = "ralink,rt2880-reset";
#reset-cells = <1>;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
......@@ -28,6 +25,14 @@
compatible = "mti,cpu-interrupt-controller";
};
clk48m: clk48m@0 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
palmbus@10000000 {
compatible = "palmbus", "simple-bus";
reg = <0x10000000 0x200000>;
......@@ -48,11 +53,175 @@
mask = <0x1>;
};
clkctrl: clkctrl@0x2c {
reg = <0x2c 0x8>, <0x10 0x4>;
reg-names = "syscfg0", "clkcfg";
compatible = "mediatek,mt7628-clk";
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
rstctrl: rstctrl@0x34 {
reg = <0x34 0x4>;
compatible = "mediatek,mtmips-reset";
#reset-cells = <1>;
};
pinctrl: pinctrl@60 {
compatible = "mediatek,mt7628-pinctrl";
reg = <0x3c 0x2c>, <0x1300 0x100>;
reg-names = "gpiomode", "padconf";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pin_state {
};
spi_single_pins: spi_single_pins {
groups = "spi";
function = "spi";
};
spi_dual_pins: spi_dual_pins {
spi_master_pins {
groups = "spi";
function = "spi";
};
spi_cs1_pin {
groups = "spi cs1";
function = "spi cs1";
};
};
uart0_pins: uart0_pins {
groups = "uart0";
function = "uart0";
};
uart1_pins: uart1_pins {
groups = "uart1";
function = "uart1";
};
uart2_pins: uart2_pins {
groups = "uart2";
function = "uart2";
};
i2c_pins: i2c_pins {
groups = "i2c";
function = "i2c";
};
ephy_iot_mode: ephy_iot_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
ephy0_en {
groups = "ephy0";
function = "enable";
};
};
ephy_router_mode: ephy_router_mode {
ephy4_1_en {
groups = "ephy4_1_pad";
function = "analog";
};
ephy0_en {
groups = "ephy0";
function = "enable";
};
};
sd_iot_mode: sd_iot_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
sdxc_en {
groups = "sdmode";
function = "sdxc";
};
sdxc_iot_mode {
groups = "sd router";
function = "iot";
};
sd_clk_pad {
pins = "sd_clk";
drive-strength-4g = <8>;
};
};
sd_router_mode: sd_router_mode {
sdxc_router_mode {
groups = "sd router";
function = "router";
};
sdxc_map_pins {
groups = "gpio0", "i2s", "sdmode", \
"i2c", "uart1";
function = "gpio";
};
sd_clk_pad {
pins = "gpio0";
drive-strength-28 = <8>;
};
};
emmc_iot_8bit_mode: emmc_iot_8bit_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
emmc_en {
groups = "sdmode";
function = "sdxc";
};
emmc_iot_mode {
groups = "sd router";
function = "iot";
};
emmc_d4_d5 {
groups = "uart2";
function = "sdxc d5 d4";
};
emmc_d6 {
groups = "pwm1";
function = "sdxc d6";
};
emmc_d7 {
groups = "pwm0";
function = "sdxc d7";
};
sd_clk_pad {
pins = "sd_clk";
drive-strength-4g = <8>;
};
};
};
watchdog: watchdog@100 {
compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt";
reg = <0x100 0x30>;
resets = <&resetc 8>;
resets = <&rstctrl MT7628_TIMER_RST>;
reset-names = "wdt";
interrupt-parent = <&intc>;
......@@ -66,7 +235,7 @@
interrupt-controller;
#interrupt-cells = <1>;
resets = <&resetc 9>;
resets = <&rstctrl MT7628_INT_RST>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
......@@ -89,6 +258,9 @@
compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
reg = <0x600 0x100>;
resets = <&rstctrl MT7628_PIO_RST>;
reset-names = "pio";
interrupt-parent = <&intc>;
interrupts = <6>;
......@@ -117,17 +289,26 @@
spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x40>;
resets = <&rstctrl MT7628_SPI_RST>;
reset-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <200000000>;
clocks = <&clkctrl CLK_SPI>;
};
uart0: uartlite@c00 {
compatible = "ns16550a";
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xc00 0x100>;
resets = <&resetc 12>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
clocks = <&clkctrl CLK_UART0>;
resets = <&rstctrl MT7628_UART0_RST>;
reset-names = "uart0";
interrupt-parent = <&intc>;
......@@ -137,10 +318,15 @@
};
uart1: uart1@d00 {
compatible = "ns16550a";
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xd00 0x100>;
resets = <&resetc 19>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
clocks = <&clkctrl CLK_UART1>;
resets = <&rstctrl MT7628_UART1_RST>;
reset-names = "uart1";
interrupt-parent = <&intc>;
......@@ -150,10 +336,15 @@
};
uart2: uart2@e00 {
compatible = "ns16550a";
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xe00 0x100>;
resets = <&resetc 20>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
clocks = <&clkctrl CLK_UART2>;
resets = <&rstctrl MT7628_UART2_RST>;
reset-names = "uart2";
interrupt-parent = <&intc>;
......@@ -163,11 +354,14 @@
};
};
eth@10110000 {
eth: eth@10110000 {
compatible = "mediatek,mt7628-eth";
reg = <0x10100000 0x10000
0x10110000 0x8000>;
resets = <&rstctrl MT7628_EPHY_RST>;
reset-names = "ephy";
syscon = <&sysc>;
};
......@@ -178,8 +372,12 @@
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
resets = <&resetc 22 &resetc 25>;
reset-names = "host", "device";
resets = <&rstctrl MT7628_UPHY_RST>;
reset-names = "phy";
clocks = <&clkctrl CLK_UPHY>;
clock-names = "cg";
};
ehci@101c0000 {
......@@ -192,4 +390,18 @@
interrupt-parent = <&intc>;
interrupts = <18>;
};
mmc: mmc@10130000 {
compatible = "mediatek,mt7620-mmc";
reg = <0x10130000 0x4000>;
builtin-cd = <1>;
r_smpl = <1>;
clocks = <&clk48m>, <&clkctrl CLK_SDXC>;
clock-names = "source", "hclk";
resets = <&rstctrl MT7628_SDXC_RST>;
status = "disabled";
};
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*/
/dts-v1/;
......
......@@ -87,7 +87,7 @@ static inline unsigned long scache_line_size(void)
#ifdef CONFIG_MIPS_L2_CACHE
return gd->arch.l2_line_size;
#else
return 0;
return CONFIG_SYS_SCACHE_LINE_SIZE;
#endif
}
......
......@@ -13,6 +13,8 @@ choice
config SOC_MT7628
bool "MT7628"
select MIPS_L1_CACHE_SHIFT_5
select PINCTRL_MT7628
select MTK_SERIAL
help
This supports MediaTek MT7628/MT7688.
......
NETGEAR DGND3700V2 BOARD
M: Álvaro Fernández Rojas <noltari@gmail.com>
M: Álvaro Fernández Rojas <noltari@gmail.com>
S: Maintained
F: board/netgear/dgnd3700v2/
F: include/configs/netgear_dgnd3700v2.h
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
*/
#include <common.h>
......
......@@ -25,6 +25,7 @@ CONFIG_CMD_LICENSE=y
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
......@@ -37,6 +38,10 @@ CONFIG_DM_GPIO=y
CONFIG_LED=y
CONFIG_LED_BCM6328=y
CONFIG_LED_BLINK=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6368=y
CONFIG_DM_ETH=y
CONFIG_BCM6368_ETH=y
CONFIG_PHY=y
......
......@@ -45,7 +45,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
......@@ -60,14 +59,8 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_BEB_LIMIT=22
CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_SYSRESET_SYSCON=y
......
......@@ -48,7 +48,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
......@@ -63,14 +62,8 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_BEB_LIMIT=22
CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
CONFIG_POWER_DOMAIN=y
CONFIG_RAM=y
CONFIG_DM_RESET=y