GitLab

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

TODO: Add bloat-o-meter comment and explain why.

This goes upstream.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

The driver currently creates a broken topology,
with a source-to-source link and a sink-to-sink
link instead of two source-to-sink links.
Reported-by: Nicolas Dufresne <nicolas@ndufresne.ca>
Cc: <stable@vger.kernel.org>      # for v5.3 and up
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

These are bits so to test if a pad is a sink you use & but not ==.

It looks like the only reason this hasn't caused problems before is that
media_get_pad_index() is currently only used with pads that do not set the
MEDIA_PAD_FL_MUST_CONNECT flag. So a pad really had only the SINK or SOURCE
flag set and nothing else.
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Cc: <stable@vger.kernel.org>      # for v5.3 and up

Use WARN_ON instead of BUG_ON.

Add two new WARN_ONs to verify that the source pad is really a source
and that the sink pad is really a sink.
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

The topology that v4l2_m2m_register_media_controller() creates for a
processing block actually created a source-to-source link and a sink-to-sink
link instead of two source-to-sink links.

Unfortunately v4l2-compliance never checked for such bad links, so this
went unreported for quite some time.
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Reported-by: Nicolas Dufresne <nicolas@ndufresne.ca>
Cc: <stable@vger.kernel.org>      # for v4.19 and up

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
decoder cores and a reset/control block.

Hook up the bus clock to the VPU power domain to enable handshakes, and
configure the core clocks to 600 MHz and the bus clock to 800 MHz by
default.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

For now this just enables MPEG-2 decoding on the Hantro G1 on i.MX8MQ.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Add devicetree binding documentation for the Hantro G1/G2 VPU on i.MX8MQ
and for the Hantro G1/G2/H1 VPU on i.MX8MM.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

This is stalling my boot.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>

Add VIP HW type to avoid GPU/VIP command mess when run VX/CL apps.

Date: 4 Dec, 2019
Singed-off-by: Ella Feng <ella.feng@nxp.com>

This enables SOF for i.MX8QXP.

    Brings in support for:
            * IMX DSP protocol communication driver
            * SOF_OF, device tree support for SOF
            * SOF_IMX8, support for i.MX8QXP integration.
            * Generic FSL DAI support
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

Mark ocotp as read only, if you need to program fuse in linux,
remove this property.
Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

The previous offset / 4 maps to fuse map row index, which is
not friendly for user. So align with the following patch, update
the write to align with fuse row index exactly

"
    nvmem: imx: correct the fuse word index

    iMX8 fuse word index represent as one 4-bytes word,
    it should not be divided by 4.

    Exp:
    - MAC0 address layout in fuse:
    offset 708: MAC[3] MAC[2] MAC[1] MAC[0]
    offset 709: XX     xx     MAC[5] MAC[4]
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
"
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

SIP number 0xC200000A is for reading, 0xC200000B is for writing.
And the following two args for write are word index, data to write.

Fixes: 885ce72a ("nvmem: imx: scu: support write")
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

The fuse programming from non-secure world is blocked, so we could
only use Arm Trusted Firmware SIP call to let ATF program fuse.

Because there is ECC region that could only be programmed once,
so add a heler in_ecc to check the ecc region.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20191029114240.14905-5-srinivas.kandagatla@linaro.orgSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Introduce HOLE/ECC_REGION flag and in_hole helper to ease the check
of hole region. The ECC_REGION is also introduced here which is
preparing for programming support. ECC_REGION could only be programmed
once, so need take care.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20191029114240.14905-4-srinivas.kandagatla@linaro.orgSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Support Qbv/Qci/Qbu/Credit Base Shaper etc.
This patch using the generic netlink adapt layer driver net/tsn/*
and include/net/tsn.h interface load by user space. The user space
refer the include/uapi/linux/tsn.h.
Signed-off-by: Po Liu <Po.Liu@nxp.com>

The ENETC hardware support the Credit Based Shaper(CBS) which part
of the IEEE-802.1Qav. The CBS driver was loaded by the sch_cbs
interface when set in the QOS in the kernel.

Here is an example command to set 20Mbits bandwidth in 1Gbits port
for taffic class 7:

tc qdisc add dev eth0 root handle 1: mqprio \
	   num_tc 8 map 0 1 2 3 4 5 6 7 hw 1

tc qdisc replace dev eth0 parent 1:8 cbs \
	   locredit -1470 hicredit 30 \
	   sendslope -980000 idleslope 20000 offload 1
Signed-off-by: Po Liu <Po.Liu@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

increase CMA size to 160MB to fix cma alloc failure for v4l2 capture case:

Capture_To_Display_mmap: mode 6(2592x1944)@15fps test.
...
[ 247.301290] cma: cma_alloc: alloc failed, req-size: 2461 pages, ret: -12
[ 247.308290] mx6s-csi 21c4000.csi: dma_alloc_coherent of size 10080256 failed
[ 247.317097] cma: cma_alloc: alloc failed, req-size: 2461 pages, ret: -12
...
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
(cherry picked from commit 1b0a2c9d50ac0d441243f0a2e88760c7e1e7b5ef)

On i.MX6QP, the soc_id exported to the /sys/devices/soc0/soc_id
should be 'i.MX6QP'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>

The i.MX8QM/QXP LDB control register lives in CSR region, so the offset
of it should be calculated according to CSR region start address.
Without this patch, the offset is calculated according to i.MX8QM/QXP
LVDS subsystem start address.  This patch corrects the offset.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

Registers tx_ulps and pxl2dpi live in CSR region, so the offsets of
them should be calculated according to CSR region start address.
Without this patch, the offsets are calculated according to i.MX8QM
MIPI DSI subsystem start address or i.MX8QXP LVDS/MIPI DSI subsystem
start address.  This patch corrects the offsets.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

The LVDS/MIPI DSI region is the CSR(Control Status Registers) space.
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address.  However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs.  This patch corrects the LVDS/MIPI DSI
region start address and chooses a sensible size, which makes sure all
exposed registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address.  However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs.  This patch corrects the MIPI CSR
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

The LVDS region is the CSR(Control Status Registers) space.
The spec tells us that the CSR start address is 0x1000 and end address
is 0x1FFF according to the subsystem start address.  However, it turns
out some space are inaccessible, which would accidently cause system
hang via kernel regmap debugfs.  This patch corrects the LVDS region
start address and chooses a sensible size, which makes sure all exposed
registers are accessible.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

The channel num (9 - 15) should not be supported in tdm & daisy chain
mode for there is two dataline, this channel number can't be
symmetrically distributed on two dataline (the first one is fixed to
be 8 channel)

Fixes commit 8d298743 ("MLK-17817-2: ASoC: imx-ak4458: enable 16
channels in TDM mode")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 0bc47b31)

Create a new dts to support rm67191 panel display and its
touch function on the imx8mm ddr4 evk revb board.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

There are some fallthrough build warnings reported by
the GCC with -Wimplicit-fallthrough option like below:

drivers/gpu/drm/bridge/sec-dsim.c: In function ‘sec_mipi_dsim_write_pl_to_sfr_fifo’:
drivers/gpu/drm/bridge/sec-dsim.c:606:11: warning: this statement may fall through [-Wimplicit-fallthrough=]
  606 |   pl_data |= ((u8 *)payload)[2] << 16;
      |   ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/sec-dsim.c:607:2: note: here
  607 |  case 2:
      |  ^~~~
drivers/gpu/drm/bridge/sec-dsim.c:608:11: warning: this statement may fall through [-Wimplicit-fallthrough=]
  608 |   pl_data |= ((u8 *)payload)[1] << 8;
      |   ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/sec-dsim.c:609:2: note: here
  609 |  case 1:
      |  ^~~~
drivers/gpu/drm/bridge/sec-dsim.c: In function ‘sec_mipi_dsim_read_pl_from_sfr_fifo’:
drivers/gpu/drm/bridge/sec-dsim.c:687:24: warning: this statement may fall through [-Wimplicit-fallthrough=]
  687 |     ((u8 *)payload)[2] = (pl >> 16) & 0xff;
      |     ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/sec-dsim.c:688:4: note: here
  688 |    case 2:
      |    ^~~~
drivers/gpu/drm/bridge/sec-dsim.c:689:24: warning: this statement may fall through [-Wimplicit-fallthrough=]
  689 |     ((u8 *)payload)[1] = (pl >> 8) & 0xff;
      |     ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~
drivers/gpu/drm/bridge/sec-dsim.c:690:4: note: here
  690 |    case 1:
      |    ^~~~
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>

To be used with SOF.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

This will support ESAI + cs42888 usecase.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

This enables SOF for i.MX8QXP.

Brings in support for:
	* IMX DSP protocol communication driver
	* SOF_OF, device tree support for SOF
	* SOF_IMX8, support for i.MX8QXP integration.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

This aligns DSP node description with upstream. No need
to add backward compatibility for older dtbs because
FSL DSP driver is obsolete and it will be removed in the future
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>