From f95bd9e563470a51140601c4c1fb54cccb14f55a Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Wed, 30 Apr 2025 20:01:09 +0200
Subject: [PATCH] [DEBUG] arm64: dts: rockchip: rock5bp: enable vsync debug
gpio
Enable vsync GPIOs for the second camera/display.
On a Rock 5B+ this means:
Pin 1 = 3.3V
Pin 3 = ISP0 frame start
Pin 5 = ISP0 frame end
Pin 7 = VP0 vsync
Pin 9 = GND
Pin 11 = ISP1 frame start
Pin 13 = ISP1 frame end
Pin 15 = VP1 vsync
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../boot/dts/rockchip/rk3588-rock-5b-imx415-port2.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-imx415-port2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-imx415-port2.dtsi
index ac242d15ffa06..f3685ca10bc8d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-imx415-port2.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-imx415-port2.dtsi
@@ -106,6 +106,9 @@ mipi4_csi2_output: endpoint@0 {
};
&rkcif {
+ /* pin 11 and 13 on the pin header */
+ isp1-frame-start-notify-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; /* pin 11 on pin header */
+ isp1-frame-end-notify-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; /* pin 13 on pin header */
status = "okay";
};
@@ -154,3 +157,7 @@ isp1_vir1: endpoint@0 {
};
};
};
+
+&vp1 {
+ vsync-notify-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; /* pin 15 on pin header */
+};
--
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