Commit 61e02392 authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
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locking/atomic/bitops: Document and clarify ordering semantics for failed test_and_{}_bit()

A test_and_{}_bit() operation fails if the value of the bit is such that
the modification does not take place. For example, if test_and_set_bit()
returns 1. In these cases, follow the behaviour of cmpxchg and allow the
operation to be unordered. This also applies to test_and_set_bit_lock()
if the lock is found to be be taken already.
Signed-off-by: default avatarWill Deacon <>
Acked-by: default avatarPeter Zijlstra (Intel) <>
Cc: Linus Torvalds <>
Cc: Paul E. McKenney <>
Cc: Thomas Gleixner <>

Signed-off-by: default avatarIngo Molnar <>
parent 11dc1322
......@@ -58,7 +58,12 @@ Like with atomic_t, the rule of thumb is:
- RMW operations that have a return value are fully ordered.
Except for test_and_set_bit_lock() which has ACQUIRE semantics and
- RMW operations that are conditional are unordered on FAILURE,
otherwise the above rules apply. In the case of test_and_{}_bit() operations,
if the bit in memory is unchanged by the operation then it is deemed to have
Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and
clear_bit_unlock() which has RELEASE semantics.
Since a platform only has a single means of achieving atomic operations
......@@ -7,7 +7,8 @@
* @nr: Bit to set
* @addr: Address to count from
* This operation is atomic and provides acquire barrier semantics.
* This operation is atomic and provides acquire barrier semantics if
* the returned value is 0.
* It can be used to implement bit locks.
#define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr)
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