Commit c1eaf3ce authored by Stephen Rothwell's avatar Stephen Rothwell

Merge remote-tracking branch 'asm-generic/master'

parents e98d872c b53bc17e

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......@@ -1564,6 +1564,11 @@ W:
D: bug toaster (A1 sauce makes all the difference)
D: Random linux hacker
N: James Hogan
D: Metag architecture maintainer
D: TZ1090 SoC maintainer
N: Tim Hockin
......@@ -66,8 +66,6 @@ backlight/
- directory with info on controlling backlights in flat panel displays
- Block-layer cache on fast SSDs to improve slow (raid) I/O performance.
- directory with documentation for the Blackfin arch.
- info on the Block I/O (BIO) layer.
......@@ -114,8 +112,6 @@ cputopology.txt
- documentation on how CPU topology info is exported via sysfs.
- brief tutorial on CRC computation
- directory with info about Linux on CRIS architecture.
- directory with info on the Crypto API.
......@@ -172,8 +168,6 @@ fmc/
- information about the FMC bus abstraction
- FPGA Manager Core.
- Fujitsu FR-V Linux documentation.
- info on requeueing of tasks from a non-PI futex to a PI futex
......@@ -276,8 +270,6 @@ memory-hotplug.txt
- Hotpluggable memory support, how to use and current status.
- info on MEN chameleon bus.
- directory with info about Linux on Meta architecture.
- Intel Many Integrated Core (MIC) architecture device driver.
......@@ -286,8 +278,6 @@ misc-devices/
- directory with info about devices using the misc dev subsystem
- directory with info about the MMC subsystem
- directory with info about the mn10300 architecture port
- directory with info about memory technology devices (flash)
......@@ -26,8 +26,8 @@ On what hardware does it run?
Although originally developed first for 32-bit x86-based PCs (386 or higher),
today Linux also runs on (at least) the Compaq Alpha AXP, Sun SPARC and
UltraSPARC, Motorola 68000, PowerPC, PowerPC64, ARM, Hitachi SuperH, Cell,
IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64, AXIS CRIS,
Xtensa, Tilera TILE, ARC and Renesas M32R architectures.
IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64 Xtensa, and
ARC architectures.
Linux is easily portable to most general-purpose 32- or 64-bit architectures
as long as they have a paged memory management unit (PMMU) and a port of the
......@@ -89,7 +89,6 @@ parameter is applicable::
APM Advanced Power Management support is enabled.
ARM ARM architecture is enabled.
AX25 Appropriate AX.25 support is enabled.
BLACKFIN Blackfin architecture is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
DRM Direct Rendering Management support is enabled.
......@@ -1025,7 +1025,7 @@
address. The serial port must already be setup
and configured. Options are not yet supported.
earlyprintk= [X86,SH,BLACKFIN,ARM,M68k,S390]
earlyprintk= [X86,SH,ARM,M68k,S390]
......@@ -1347,10 +1347,6 @@
If specified, z/VM IUCV HVC accepts connections
from listed z/VM user IDs only.
hwthread_map= [METAG] Comma-separated list of Linux cpu id to
hardware thread id mappings.
Format: <cpu>:<hwthread>
keep_bootcon [KNL]
Do not unregister boot console at start. This is only
useful for debugging when something happens in the window
- This file
- Notes in developing/using bfin-gpio driver.
- Notes for using bfin spi bus driver.
* File: Documentation/blackfin/bfin-gpio-notes.txt
* Based on:
* Author:
* Created: $Id: bfin-gpio-note.txt 2008-11-24 16:42 grafyang $
* Description: This file contains the notes in developing/using bfin-gpio.
* Rev:
* Modified:
* Copyright 2004-2008 Analog Devices Inc.
* Bugs: Enter bugs at
1. Blackfin GPIO introduction
There are many GPIO pins on Blackfin. Most of these pins are muxed to
multi-functions. They can be configured as peripheral, or just as GPIO,
configured to input with interrupt enabled, or output.
For detailed information, please see "arch/blackfin/kernel/bfin_gpio.c",
or the relevant HRM.
2. Avoiding resource conflict
Followed function groups are used to avoiding resource conflict,
- Use the pin as peripheral,
int peripheral_request(unsigned short per, const char *label);
int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free(unsigned short per);
void peripheral_free_list(const unsigned short per[]);
- Use the pin as GPIO,
int bfin_gpio_request(unsigned gpio, const char *label);
void bfin_gpio_free(unsigned gpio);
- Use the pin as GPIO interrupt,
int bfin_gpio_irq_request(unsigned gpio, const char *label);
void bfin_gpio_irq_free(unsigned gpio);
The request functions will record the function state for a certain pin,
the free functions will clear its function state.
Once a pin is requested, it can't be requested again before it is freed by
previous caller, otherwise kernel will dump stacks, and the request
function fail.
These functions are wrapped by other functions, most of the users need not
3. But there are some exceptions
- Kernel permit the identical GPIO be requested both as GPIO and GPIO
Some drivers, like gpio-keys, need this behavior. Kernel only print out
warning messages like,
bfin-gpio: GPIO 24 is already reserved by gpio-keys: BTN0, and you are
configuring it as IRQ!
Note: Consider the case that, if there are two drivers need the
identical GPIO, one of them use it as GPIO, the other use it as
GPIO interrupt. This will really cause resource conflict. So if
there is any abnormal driver behavior, please check the bfin-gpio
warning messages.
- Kernel permit the identical GPIO be requested from the same driver twice.
SPI Chip Select behavior:
With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
bit whether the Slave Select Line is controlled by hardware (CPHA=0) or
controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that
the Slave Select is always under software control and being asserted during
the entire SPI transfer. - And not just bits_per_word duration.
In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
timing, you can utilize the GPIO controlled SPI Slave Select option instead.
In this case, you should use GPIO based CS for all of your slaves and not just
the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
You can even use the same pin whose peripheral role is a SSEL,
but use it as a GPIO instead.
Linux on the CRIS architecture
This is a port of Linux to Axis Communications ETRAX 100LX,
ETRAX FS and ARTPEC-3 embedded network CPUs.
For more information about CRIS and ETRAX please see further below.
In order to compile this you need a version of gcc with support for the
ETRAX chip family. Please see this link for more information on how to
download the compiler and other tools useful when building and booting
software for the ETRAX platform:
What is CRIS ?
CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU
architecture in Axis Communication AB's range of embedded network CPU's,
called ETRAX.
The ETRAX 100LX chip
For reference, please see the following link:
The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
range of built-in interfaces, all with modern scatter/gather DMA.
Memory interfaces:
* NOR-flash/ROM
* EDO or page-mode DRAM
I/O interfaces:
* one 10/100 Mbit/s ethernet controller
* four serial-ports (up to 6 Mbit/s)
* two synchronous serial-ports for multimedia codec's etc.
* USB host controller and USB slave
* two parallel-ports
* two generic 8-bit ports