Skip to content
Snippets Groups Projects
Select Git revision
  • 1f52247ef840db6ddd727fb1bd1c38b7153120c3
  • linus-master default
  • kunit_is_love
  • kunit_drm
  • tonyk/futex_waitv
  • hidraw_rwlock
  • futex_waitv
  • futex2-dev
  • idle_sleep
  • futex2-proton
  • futex-tests
  • futex2
  • futex2-numa
  • fwm-5.11
  • cf-fix
  • tmpfs-ic
  • futex2-stable-5.11
  • futex2-stable
  • futex2-lpc
  • gaming
  • futex-fixes
21 results

linux

  • Clone with SSH
  • Clone with HTTPS
  • user avatar
    David S. Miller authored
    Vladimir Oltean says:
    
    ====================
    NXP SJA1105 driver support for "H" switch topologies
    
    Changes in v3:
    Preserve the behavior of dsa_tree_setup_default_cpu() which is to pick
    the first CPU port and not the last.
    
    Changes in v2:
    Send as non-RFC, drop the patches for discarding DSA-tagged packets on
    user ports and DSA-untagged packets on DSA and CPU ports for now.
    
    NXP builds boards like the Bluebox 3 where there are multiple SJA1110
    switches connected to an LX2160A, but they are also connected to each
    other. I call this topology an "H" tree because of the lateral
    connection between switches. A piece extracted from a non-upstream
    device tree looks like this:
    
    &spi_bridge {
            /* SW1 */
            ethernet-switch@0 {
                    compatible = "nxp,sja1110a";
                    reg = <0>;
                    dsa,member = <0 0>;
    
                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
    
                            /* SW1_P1 */
                            port@1 {
                                    reg = <1>;
                                    label = "con_2x20";
                                    phy-mode = "sgmii";
    
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
    
                            port@2 {
                                    reg = <2>;
                                    ethernet = <&dpmac17>;
                                    phy-mode = "rgmii-id";
    
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
    
                            port@3 {
                                    reg = <3>;
                                    label = "1ge_p1";
                                    phy-mode = "rgmii-id";
                                    phy-handle = <&sw1_mii3_phy>;
                            };
    
                            sw1p4: port@4 {
                                    reg = <4>;
                                    link = <&sw2p1>;
                                    phy-mode = "sgmii";
    
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
    
                            port@5 {
                                    reg = <5>;
                                    label = "trx1";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port5_base_t1_phy>;
                            };
    
                            port@6 {
                                    reg = <6>;
                                    label = "trx2";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port6_base_t1_phy>;
                            };
    
                            port@7 {
                                    reg = <7>;
                                    label = "trx3";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port7_base_t1_phy>;
                            };
    
                            port@8 {
                                    reg = <8>;
                                    label = "trx4";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port8_base_t1_phy>;
                            };
    
                            port@9 {
                                    reg = <9>;
                                    label = "trx5";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port9_base_t1_phy>;
                            };
    
                            port@a {
                                    reg = <10>;
                                    label = "trx6";
                                    phy-mode = "internal";
                                    phy-handle = <&sw1_port10_base_t1_phy>;
                            };
                    };
            };
    
            /* SW2 */
            ethernet-switch@2 {
                    compatible = "nxp,sja1110a";
                    reg = <2>;
                    dsa,member = <0 1>;
    
                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
    
                            sw2p1: port@1 {
                                    reg = <1>;
                                    link = <&sw1p4>;
                                    phy-mode = "sgmii";
    
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
    
                            port@2 {
                                    reg = <2>;
                                    ethernet = <&dpmac18>;
                                    phy-mode = "rgmii-id";
    
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
    
                            port@3 {
                                    reg = <3>;
                                    label = "1ge_p2";
                                    phy-mode = "rgmii-id";
                                    phy-handle = <&sw2_mii3_phy>;
                            };
    
                            port@4 {
                                    reg = <4>;
                                    label = "to_sw3";
                                    phy-mode = "2500base-x";
    
                                    fixed-link {
                                            speed = <2500>;
                                            full-duplex;
                                    };
                            };
    
                            port@5 {
                                    reg = <5>;
                                    label = "trx7";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port5_base_t1_phy>;
                            };
    
                            port@6 {
                                    reg = <6>;
                                    label = "trx8";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port6_base_t1_phy>;
                            };
    
                            port@7 {
                                    reg = <7>;
                                    label = "trx9";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port7_base_t1_phy>;
                            };
    
                            port@8 {
                                    reg = <8>;
                                    label = "trx10";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port8_base_t1_phy>;
                            };
    
                            port@9 {
                                    reg = <9>;
                                    label = "trx11";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port9_base_t1_phy>;
                            };
    
                            port@a {
                                    reg = <10>;
                                    label = "trx12";
                                    phy-mode = "internal";
                                    phy-handle = <&sw2_port10_base_t1_phy>;
                            };
                    };
            };
    };
    
    Basically it is a single DSA tree with 2 "ethernet" properties, i.e. a
    multi-CPU-port system. There is also a DSA link between the switches,
    but it is not a daisy chain topology, i.e. there is no "upstream" and
    "downstream" switch, the DSA link is only to be used for the bridge data
    plane (autonomous forwarding between switches, between the RJ-45 ports
    and the automotive Ethernet ports), otherwise all traffic that should
    reach the host should do so through the dedicated CPU port of the switch.
    
    Of course, plain forwarding in this topology is bound to create packet
    loops. I have thought long and hard about strategies to cut forwarding
    in such a way as to prevent loops but also not impede normal operation
    of the network on such a system, and I believe I have found a solution
    that does work as expected. This relies heavily on DSA's recent ability
    to perform RX filtering towards the host by installing MAC addresses as
    static FDB entries. Since we have 2 distinct DSA masters, we have 2
    distinct MAC addresses, and if the bridge is configured to have its own
    MAC address that makes it 3 distinct MAC addresses. The bridge core,
    plus the switchdev_handle_fdb_add_to_device() extension, handle each MAC
    address by replicating it to each port of the DSA switch tree. So the
    end result is that both switch 1 and switch 2 will have static FDB
    entries towards their respective CPU ports for the 3 MAC addresses
    corresponding to the DSA masters and to the bridge net device (and of
    course, towards any station learned on a foreign interface).
    
    So I think the basic design works, and it is basically just as fragile
    as any other multi-CPU-port system is bound to be in terms of reliance
    on static FDB entries towards the host (if hardware address learning on
    the CPU port is to be used, MAC addresses would randomly bounce between
    one CPU port and the other otherwise). In fact, I think it is even
    better to start DSA's support of multi-CPU-port systems with something
    small like the NXP Bluebox 3, because we allow some time for the code
    paths like dsa_switch_host_address_match(), which were specifically
    designed for it, to break in, and this board needs no user space
    configuration of CPU ports, like static assignments between user and CPU
    ports, or bonding between the CPU ports/DSA masters.
    ====================
    
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    1f52247e
    History
    Name Last commit Last update