Commit 59fb59ad authored by Jason Ekstrand's avatar Jason Ekstrand Committed by Jordan Justen

nir: Get rid of nir_shader::stage

It's redundant with nir_shader::info::stage.
Acked-by: default avatarTimothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Reviewed-by: default avatarJordan Justen <jordan.l.justen@intel.com>
parent 341529db
......@@ -6453,7 +6453,7 @@ static unsigned
ac_nir_get_max_workgroup_size(enum chip_class chip_class,
const struct nir_shader *nir)
{
switch (nir->stage) {
switch (nir->info.stage) {
case MESA_SHADER_TESS_CTRL:
return chip_class >= CIK ? 128 : 64;
case MESA_SHADER_GEOMETRY:
......@@ -6510,7 +6510,7 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
if (nctx)
nctx->nir = &ctx;
ctx.stage = nir->stage;
ctx.stage = nir->info.stage;
ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
......@@ -6528,7 +6528,7 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
setup_locals(&ctx, func);
if (nir->stage == MESA_SHADER_COMPUTE)
if (nir->info.stage == MESA_SHADER_COMPUTE)
setup_shared(&ctx, nir);
visit_cf_list(&ctx, &func->impl->body);
......@@ -6586,8 +6586,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.max_workgroup_size = ac_nir_get_max_workgroup_size(ctx.options->chip_class, shaders[0]);
create_function(&ctx, shaders[shader_count - 1]->stage, shader_count >= 2,
shader_count >= 2 ? shaders[shader_count - 2]->stage : MESA_SHADER_VERTEX);
create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
ctx.abi.inputs = &ctx.inputs[0];
ctx.abi.emit_outputs = handle_shader_outputs_post;
......@@ -6598,28 +6598,28 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ac_init_exec_full_mask(&ctx.ac);
if (ctx.ac.chip_class == GFX9 &&
shaders[shader_count - 1]->stage == MESA_SHADER_TESS_CTRL)
shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
ac_nir_fixup_ls_hs_input_vgprs(&ctx);
for(int i = 0; i < shader_count; ++i) {
ctx.stage = shaders[i]->stage;
ctx.stage = shaders[i]->info.stage;
ctx.output_mask = 0;
ctx.tess_outputs_written = 0;
ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.i32, "gs_next_vertex");
ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
} else if (shaders[i]->stage == MESA_SHADER_TESS_EVAL) {
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
} else if (shaders[i]->stage == MESA_SHADER_VERTEX) {
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
ctx.shader_info->vs.vgpr_comp_cnt =
MAX2(3, ctx.shader_info->vs.vgpr_comp_cnt);
}
} else if (shaders[i]->stage == MESA_SHADER_FRAGMENT) {
} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
}
......@@ -6645,15 +6645,15 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
}
if (shaders[i]->stage == MESA_SHADER_FRAGMENT)
if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
handle_fs_inputs(&ctx, shaders[i]);
else if(shaders[i]->stage == MESA_SHADER_VERTEX)
else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
handle_vs_inputs(&ctx, shaders[i]);
else if(shader_count >= 2 && shaders[i]->stage == MESA_SHADER_GEOMETRY)
else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
prepare_gs_input_vgprs(&ctx);
nir_foreach_variable(variable, &shaders[i]->outputs)
scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->stage);
scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
......@@ -6662,16 +6662,16 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
}
if (shaders[i]->stage == MESA_SHADER_GEOMETRY) {
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
unsigned addclip = shaders[i]->info.clip_distance_array_size +
shaders[i]->info.cull_distance_array_size > 4;
shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
shaders[i]->info.gs.vertices_out;
} else if (shaders[i]->stage == MESA_SHADER_TESS_CTRL) {
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.outputs_written = ctx.tess_outputs_written;
shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
} else if (shaders[i]->stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
shader_info->vs.outputs_written = ctx.tess_outputs_written;
}
}
......@@ -6815,7 +6815,7 @@ static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
static void
ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
{
switch (nir->stage) {
switch (nir->info.stage) {
case MESA_SHADER_COMPUTE:
for (int i = 0; i < 3; ++i)
shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
......@@ -6864,7 +6864,7 @@ void ac_compile_nir_shader(LLVMTargetMachineRef tm,
LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
options);
ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->stage, dump_shader, options->supports_spill);
ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
for (int i = 0; i < nir_count; ++i)
ac_fill_shader_info(shader_info, nir[i], options);
}
......
......@@ -116,7 +116,7 @@ gather_info_input_decl(nir_shader *nir,
nir_variable *var,
struct ac_shader_info *info)
{
switch (nir->stage) {
switch (nir->info.stage) {
case MESA_SHADER_VERTEX:
info->vs.has_vertex_buffers = true;
break;
......
......@@ -208,7 +208,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
spec_entries, num_spec_entries,
stage, entrypoint_name, &supported_ext, &nir_options);
nir = entry_point->shader;
assert(nir->stage == stage);
assert(nir->info.stage == stage);
nir_validate_shader(nir);
free(spec_entries);
......@@ -258,9 +258,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
* indirect indexing is trivial.
*/
nir_variable_mode indirect_mask = 0;
if (nir->stage == MESA_SHADER_GEOMETRY ||
(nir->stage != MESA_SHADER_TESS_CTRL &&
nir->stage != MESA_SHADER_TESS_EVAL &&
if (nir->info.stage == MESA_SHADER_GEOMETRY ||
(nir->info.stage != MESA_SHADER_TESS_CTRL &&
nir->info.stage != MESA_SHADER_TESS_EVAL &&
!llvm_has_working_vgpr_indexing)) {
indirect_mask |= nir_var_shader_in;
}
......@@ -504,7 +504,7 @@ radv_shader_variant_create(struct radv_device *device,
options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
options.supports_spill = device->llvm_supports_spill;
return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->stage,
return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
&options, false, code_out, code_size_out);
}
......
......@@ -1375,7 +1375,7 @@ ntq_setup_inputs(struct v3d_compile *c)
qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
uint32_t vpm_components_queued = 0;
if (c->s->stage == MESA_SHADER_VERTEX) {
if (c->s->info.stage == MESA_SHADER_VERTEX) {
bool uses_iid = c->s->info.system_values_read &
(1ull << SYSTEM_VALUE_INSTANCE_ID);
bool uses_vid = c->s->info.system_values_read &
......@@ -1405,7 +1405,7 @@ ntq_setup_inputs(struct v3d_compile *c)
resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
(loc + 1) * 4);
if (c->s->stage == MESA_SHADER_FRAGMENT) {
if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
if (var->data.location == VARYING_SLOT_POS) {
emit_fragcoord_input(c, loc);
} else if (var->data.location == VARYING_SLOT_PNTC ||
......@@ -1433,7 +1433,7 @@ ntq_setup_inputs(struct v3d_compile *c)
}
}
if (c->s->stage == MESA_SHADER_VERTEX) {
if (c->s->info.stage == MESA_SHADER_VERTEX) {
assert(vpm_components_queued == 0);
assert(num_components == 0);
}
......@@ -1452,7 +1452,7 @@ ntq_setup_outputs(struct v3d_compile *c)
for (int i = 0; i < 4; i++)
add_output(c, loc + i, var->data.location, i);
if (c->s->stage == MESA_SHADER_FRAGMENT) {
if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
switch (var->data.location) {
case FRAG_RESULT_COLOR:
c->output_color_var[0] = var;
......@@ -1948,7 +1948,7 @@ ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
static void
nir_to_vir(struct v3d_compile *c)
{
if (c->s->stage == MESA_SHADER_FRAGMENT) {
if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
......@@ -2013,7 +2013,7 @@ void
v3d_nir_to_vir(struct v3d_compile *c)
{
if (V3D_DEBUG & (V3D_DEBUG_NIR |
v3d_debug_flag_for_shader_stage(c->s->stage))) {
v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
fprintf(stderr, "%s prog %d/%d NIR:\n",
vir_get_stage_name(c),
c->program_id, c->variant_id);
......@@ -2022,7 +2022,7 @@ v3d_nir_to_vir(struct v3d_compile *c)
nir_to_vir(c);
switch (c->s->stage) {
switch (c->s->info.stage) {
case MESA_SHADER_FRAGMENT:
emit_frag_end(c);
break;
......@@ -2034,7 +2034,7 @@ v3d_nir_to_vir(struct v3d_compile *c)
}
if (V3D_DEBUG & (V3D_DEBUG_VIR |
v3d_debug_flag_for_shader_stage(c->s->stage))) {
v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
vir_get_stage_name(c),
c->program_id, c->variant_id);
......@@ -2048,7 +2048,7 @@ v3d_nir_to_vir(struct v3d_compile *c)
/* XXX: vir_schedule_instructions(c); */
if (V3D_DEBUG & (V3D_DEBUG_VIR |
v3d_debug_flag_for_shader_stage(c->s->stage))) {
v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
fprintf(stderr, "%s prog %d/%d VIR:\n",
vir_get_stage_name(c),
c->program_id, c->variant_id);
......
......@@ -894,5 +894,5 @@ vir_get_stage_name(struct v3d_compile *c)
if (c->vs_key && c->vs_key->is_coord)
return "MESA_SHADER_COORD";
else
return gl_shader_stage_name(c->s->stage);
return gl_shader_stage_name(c->s->info.stage);
}
......@@ -349,7 +349,7 @@ v3d_vir_to_qpu(struct v3d_compile *c)
}
if (V3D_DEBUG & (V3D_DEBUG_QPU |
v3d_debug_flag_for_shader_stage(c->s->stage))) {
v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
v3d_dump_qpu(c);
}
......
......@@ -163,7 +163,7 @@ glsl_to_nir(const struct gl_shader_program *shader_prog,
* two locations. For instance, if we have in the IR code a dvec3 attr0 in
* location 0 and vec4 attr1 in location 1, in NIR attr0 will use
* locations/slots 0 and 1, and attr1 will use location/slot 2 */
if (shader->stage == MESA_SHADER_VERTEX)
if (shader->info.stage == MESA_SHADER_VERTEX)
nir_remap_attributes(shader);
shader->info.name = ralloc_asprintf(shader, "GLSL%d", shader_prog->Name);
......@@ -341,12 +341,12 @@ nir_visitor::visit(ir_variable *ir)
break;
case ir_var_shader_in:
if (shader->stage == MESA_SHADER_FRAGMENT &&
if (shader->info.stage == MESA_SHADER_FRAGMENT &&
ir->data.location == VARYING_SLOT_FACE) {
/* For whatever reason, GLSL IR makes gl_FrontFacing an input */
var->data.location = SYSTEM_VALUE_FRONT_FACE;
var->data.mode = nir_var_system_value;
} else if (shader->stage == MESA_SHADER_GEOMETRY &&
} else if (shader->info.stage == MESA_SHADER_GEOMETRY &&
ir->data.location == VARYING_SLOT_PRIMITIVE_ID) {
/* For whatever reason, GLSL IR makes gl_PrimitiveIDIn an input */
var->data.location = SYSTEM_VALUE_PRIMITIVE_ID;
......@@ -354,7 +354,7 @@ nir_visitor::visit(ir_variable *ir)
} else {
var->data.mode = nir_var_shader_in;
if (shader->stage == MESA_SHADER_TESS_EVAL &&
if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
(ir->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
ir->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)) {
var->data.compact = ir->type->without_array()->is_scalar();
......@@ -372,7 +372,7 @@ nir_visitor::visit(ir_variable *ir)
case ir_var_shader_out:
var->data.mode = nir_var_shader_out;
if (shader->stage == MESA_SHADER_TESS_CTRL &&
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
(ir->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
ir->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)) {
var->data.compact = ir->type->without_array()->is_scalar();
......
......@@ -44,8 +44,12 @@ nir_shader_create(void *mem_ctx,
shader->options = options;
if (si)
if (si) {
assert(si->stage == stage);
shader->info = *si;
} else {
shader->info.stage = stage;
}
exec_list_make_empty(&shader->functions);
exec_list_make_empty(&shader->registers);
......@@ -58,8 +62,6 @@ nir_shader_create(void *mem_ctx,
shader->num_uniforms = 0;
shader->num_shared = 0;
shader->stage = stage;
return shader;
}
......@@ -143,7 +145,7 @@ nir_shader_add_variable(nir_shader *shader, nir_variable *var)
break;
case nir_var_shared:
assert(shader->stage == MESA_SHADER_COMPUTE);
assert(shader->info.stage == MESA_SHADER_COMPUTE);
exec_list_push_tail(&shader->shared, &var->node);
break;
......@@ -162,8 +164,10 @@ nir_variable_create(nir_shader *shader, nir_variable_mode mode,
var->type = type;
var->data.mode = mode;
if ((mode == nir_var_shader_in && shader->stage != MESA_SHADER_VERTEX) ||
(mode == nir_var_shader_out && shader->stage != MESA_SHADER_FRAGMENT))
if ((mode == nir_var_shader_in &&
shader->info.stage != MESA_SHADER_VERTEX) ||
(mode == nir_var_shader_out &&
shader->info.stage != MESA_SHADER_FRAGMENT))
var->data.interpolation = INTERP_MODE_SMOOTH;
if (mode == nir_var_shader_in || mode == nir_var_uniform)
......
......@@ -1904,9 +1904,6 @@ typedef struct nir_shader {
* access plus one
*/
unsigned num_inputs, num_uniforms, num_outputs, num_shared;
/** The shader stage, such as MESA_SHADER_VERTEX. */
gl_shader_stage stage;
} nir_shader;
static inline nir_function_impl *
......
......@@ -737,7 +737,7 @@ nir_shader_clone(void *mem_ctx, const nir_shader *s)
clone_state state;
init_clone_state(&state, NULL, true, false);
nir_shader *ns = nir_shader_create(mem_ctx, s->stage, s->options, NULL);
nir_shader *ns = nir_shader_create(mem_ctx, s->info.stage, s->options, NULL);
state.ns = ns;
clone_var_list(&state, &ns->uniforms, &s->uniforms);
......
......@@ -53,7 +53,7 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len)
else
shader->info.inputs_read |= bitfield;
if (shader->stage == MESA_SHADER_FRAGMENT) {
if (shader->info.stage == MESA_SHADER_FRAGMENT) {
shader->info.fs.uses_sample_qualifier |= var->data.sample;
}
} else {
......@@ -79,7 +79,7 @@ mark_whole_variable(nir_shader *shader, nir_variable *var)
{
const struct glsl_type *type = var->type;
if (nir_is_per_vertex_io(var, shader->stage)) {
if (nir_is_per_vertex_io(var, shader->info.stage)) {
assert(glsl_type_is_array(type));
type = glsl_get_array_element(type);
}
......@@ -129,7 +129,7 @@ try_mask_partial_io(nir_shader *shader, nir_deref_var *deref)
nir_variable *var = deref->var;
const struct glsl_type *type = var->type;
if (nir_is_per_vertex_io(var, shader->stage)) {
if (nir_is_per_vertex_io(var, shader->info.stage)) {
assert(glsl_type_is_array(type));
type = glsl_get_array_element(type);
}
......@@ -196,7 +196,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader)
switch (instr->intrinsic) {
case nir_intrinsic_discard:
case nir_intrinsic_discard_if:
assert(shader->stage == MESA_SHADER_FRAGMENT);
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
shader->info.fs.uses_discard = true;
break;
......@@ -214,7 +214,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader)
/* We need to track which input_reads bits correspond to a
* dvec3/dvec4 input attribute */
if (shader->stage == MESA_SHADER_VERTEX &&
if (shader->info.stage == MESA_SHADER_VERTEX &&
var->data.mode == nir_var_shader_in &&
glsl_type_is_dual_slot(glsl_without_array(var->type))) {
for (uint i = 0; i < glsl_count_attribute_slots(var->type, false); i++) {
......@@ -252,7 +252,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader)
case nir_intrinsic_end_primitive:
case nir_intrinsic_end_primitive_with_counter:
assert(shader->stage == MESA_SHADER_GEOMETRY);
assert(shader->info.stage == MESA_SHADER_GEOMETRY);
shader->info.gs.uses_end_primitive = 1;
break;
......@@ -327,7 +327,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.patch_inputs_read = 0;
shader->info.patch_outputs_written = 0;
shader->info.system_values_read = 0;
if (shader->stage == MESA_SHADER_FRAGMENT) {
if (shader->info.stage == MESA_SHADER_FRAGMENT) {
shader->info.fs.uses_sample_qualifier = false;
}
nir_foreach_block(block, entrypoint) {
......
......@@ -75,7 +75,7 @@ tcs_add_output_reads(nir_shader *shader, uint64_t *read)
nir_variable *var = intrin_instr->variables[0]->var;
read[var->data.location_frac] |=
get_variable_io_mask(intrin_instr->variables[0]->var,
shader->stage);
shader->info.stage);
}
}
}
......@@ -102,7 +102,7 @@ remove_unused_io_vars(nir_shader *shader, struct exec_list *var_list,
uint64_t other_stage = used_by_other_stage[var->data.location_frac];
if (!(other_stage & get_variable_io_mask(var, shader->stage))) {
if (!(other_stage & get_variable_io_mask(var, shader->info.stage))) {
/* This one is invalid, make it a global variable instead */
var->data.location = 0;
var->data.mode = nir_var_global;
......@@ -120,26 +120,26 @@ remove_unused_io_vars(nir_shader *shader, struct exec_list *var_list,
bool
nir_remove_unused_varyings(nir_shader *producer, nir_shader *consumer)
{
assert(producer->stage != MESA_SHADER_FRAGMENT);
assert(consumer->stage != MESA_SHADER_VERTEX);
assert(producer->info.stage != MESA_SHADER_FRAGMENT);
assert(consumer->info.stage != MESA_SHADER_VERTEX);
uint64_t read[4] = { 0 }, written[4] = { 0 };
nir_foreach_variable(var, &producer->outputs) {
written[var->data.location_frac] |=
get_variable_io_mask(var, producer->stage);
get_variable_io_mask(var, producer->info.stage);
}
nir_foreach_variable(var, &consumer->inputs) {
read[var->data.location_frac] |=
get_variable_io_mask(var, consumer->stage);
get_variable_io_mask(var, consumer->info.stage);
}
/* Each TCS invocation can read data written by other TCS invocations,
* so even if the outputs are not used by the TES we must also make
* sure they are not read by the TCS before demoting them to globals.
*/
if (producer->stage == MESA_SHADER_TESS_CTRL)
if (producer->info.stage == MESA_SHADER_TESS_CTRL)
tcs_add_output_reads(producer, read);
bool progress = false;
......
......@@ -39,7 +39,7 @@ void
nir_lower_alpha_test(nir_shader *shader, enum compare_func func,
bool alpha_to_one)
{
assert(shader->stage == MESA_SHADER_FRAGMENT);
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
nir_foreach_function(function, shader) {
nir_function_impl *impl = function->impl;
......
......@@ -100,7 +100,7 @@ lower_instr(nir_intrinsic_instr *instr,
nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(mem_ctx, op);
nir_intrinsic_set_base(new_instr,
shader_program->data->UniformStorage[uniform_loc].opaque[shader->stage].index);
shader_program->data->UniformStorage[uniform_loc].opaque[shader->info.stage].index);
nir_load_const_instr *offset_const =
nir_load_const_instr_create(mem_ctx, 1, 32);
......
......@@ -133,7 +133,7 @@ void
nir_lower_bitmap(nir_shader *shader,
const nir_lower_bitmap_options *options)
{
assert(shader->stage == MESA_SHADER_FRAGMENT);
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
lower_bitmap_impl(nir_shader_get_entrypoint(shader), options);
}
......@@ -33,7 +33,7 @@ typedef struct {
static bool
is_color_output(lower_state *state, nir_variable *out)
{
switch (state->shader->stage) {
switch (state->shader->info.stage) {
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
switch (out->data.location) {
......
......@@ -48,7 +48,7 @@ get_unwrapped_array_length(nir_shader *nir, nir_variable *var)
* array length.
*/
const struct glsl_type *type = var->type;
if (nir_is_per_vertex_io(var, nir->stage))
if (nir_is_per_vertex_io(var, nir->info.stage))
type = glsl_get_array_element(type);
assert(glsl_type_is_array(type));
......@@ -158,7 +158,7 @@ combine_clip_cull(nir_shader *nir,
cull->data.location = VARYING_SLOT_CLIP_DIST0;
} else {
/* Turn the ClipDistance array into a combined one */
update_type(clip, nir->stage, clip_array_size + cull_array_size);
update_type(clip, nir->info.stage, clip_array_size + cull_array_size);
/* Rewrite CullDistance to reference the combined array */
nir_foreach_function(function, nir) {
......@@ -194,10 +194,10 @@ nir_lower_clip_cull_distance_arrays(nir_shader *nir)
{
bool progress = false;
if (nir->stage <= MESA_SHADER_GEOMETRY)
if (nir->info.stage <= MESA_SHADER_GEOMETRY)
progress |= combine_clip_cull(nir, &nir->outputs, true);
if (nir->stage > MESA_SHADER_VERTEX)
if (nir->info.stage > MESA_SHADER_VERTEX)
progress |= combine_clip_cull(nir, &nir->inputs, false);
return progress;
......
......@@ -252,7 +252,7 @@ nir_lower_drawpixels(nir_shader *shader,
.shader = shader,
};
assert(shader->stage == MESA_SHADER_FRAGMENT);
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
nir_foreach_function(function, shader) {
if (function->impl)
......
......@@ -167,7 +167,7 @@ lower_load(nir_intrinsic_instr *intrin, struct lower_io_state *state,
nir_intrinsic_op op;
switch (mode) {
case nir_var_shader_in:
if (nir->stage == MESA_SHADER_FRAGMENT &&
if (nir->info.stage == MESA_SHADER_FRAGMENT &&
nir->options->use_interpolated_input_intrinsics &&
var->data.interpolation != INTERP_MODE_FLAT) {
assert(vertex_index == NULL);
......@@ -412,7 +412,7 @@ nir_lower_io_block(nir_block *block,
b->cursor = nir_before_instr(instr);
const bool per_vertex = nir_is_per_vertex_io(var, b->shader->stage);
const bool per_vertex = nir_is_per_vertex_io(var, b->shader->info.stage);
nir_ssa_def *offset;
nir_ssa_def *vertex_index = NULL;
......
......@@ -76,7 +76,7 @@ emit_copies(nir_cursor cursor, nir_shader *shader, struct exec_list *new_vars,
static void
emit_output_copies_impl(struct lower_io_state *state, nir_function_impl *impl)
{
if (state->shader->stage == MESA_SHADER_GEOMETRY) {
if (state->shader->info.stage == MESA_SHADER_GEOMETRY) {
/* For geometry shaders, we have to emit the output copies right
* before each EmitVertex call.
*/
......@@ -152,7 +152,7 @@ nir_lower_io_to_temporaries(nir_shader *shader, nir_function_impl *entrypoint,
{
struct lower_io_state state;
if (shader->stage == MESA_SHADER_TESS_CTRL)
if (shader->info.stage == MESA_SHADER_TESS_CTRL)
return;
state.shader = shader;
......
......@@ -131,7 +131,7 @@ lower_io_types_block(struct lower_io_types_state *state, nir_block *block)
(var->data.mode != nir_var_shader_out))
continue;
bool vs_in = (state->shader->stage == MESA_SHADER_VERTEX) &&
bool vs_in = (state->shader->info.stage == MESA_SHADER_VERTEX) &&
(var->data.mode == nir_var_shader_in);
if (glsl_count_attribute_slots(var->type, vs_in) == 1)
continue;
......
......@@ -157,7 +157,8 @@ nir_lower_samplers(nir_shader *shader,
nir_foreach_function(function, shader) {
if (function->impl)