Commit bd25e23b authored by Jerome Glisse's avatar Jerome Glisse
Browse files

r600g: simplify states



Directly build PM4 packet, avoid using malloc (no states are
bigger than 128 dwords), remove unecessary informations,
remove pm4 building in favor of prebuild pm4 packet.
Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
parent b5c07b92
......@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
unsigned srcx, unsigned srcy, unsigned srcz,
unsigned width, unsigned height)
{
util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
src, subsrc, srcx, srcy, srcz, width, height);
}
......@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
memcpy(bo->data, vbo, 128);
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return -ENOMEM;
......@@ -199,33 +199,35 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return -ENOMEM;
}
bstates->vs_resource0 = rstate;
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
if (rstate == NULL) {
return -ENOMEM;
}
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......@@ -303,7 +305,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
......@@ -321,6 +323,8 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -374,7 +378,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
......@@ -391,6 +395,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -403,7 +408,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
rstate = radeon_state(rscreen->rw, R600_VGT);
if (rstate == NULL)
return NULL;
......@@ -425,7 +430,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
rstate = radeon_state(rscreen->rw, R600_DRAW);
if (rstate == NULL)
return NULL;
......@@ -448,7 +453,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
if (rstate == NULL)
return NULL;
......@@ -471,7 +476,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
......@@ -500,7 +505,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
rstate = radeon_state(rscreen->rw, R600_DSA);
if (rstate == NULL)
return NULL;
......@@ -524,7 +529,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
rstate = radeon_state(rscreen->rw, R600_BLEND);
if (rstate == NULL)
return NULL;
......@@ -543,7 +548,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
if (rstate == NULL)
return NULL;
......@@ -786,10 +791,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
r600_queries_suspend(ctx);
/* schedule draw*/
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
r = radeon_ctx_set_draw(rctx->ctx, draw);
if (r == -EBUSY) {
r600_flush(ctx, 0, NULL);
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
r = radeon_ctx_set_draw(rctx->ctx, draw);
}
if (r) {
goto out;
......
......@@ -53,12 +53,10 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
/* suspend queries */
r600_queries_suspend(ctx);
if (radeon_ctx_pm4(rctx->ctx))
goto out;
/* FIXME dumping should be removed once shader support instructions
* without throwing bad code
*/
if (!rctx->ctx->cpm4)
if (!rctx->ctx->id)
goto out;
sprintf(dname, "gallium-%08d.bof", dc);
if (dc < 2) {
......@@ -73,8 +71,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
}
dc++;
out:
rctx->ctx = radeon_ctx_decref(rctx->ctx);
rctx->ctx = radeon_ctx(rscreen->rw);
radeon_ctx_clear(rctx->ctx);
/* resume queries */
r600_queries_resume(ctx);
}
......@@ -218,7 +215,7 @@ static void r600_init_config(struct r600_context *rctx)
num_es_stack_entries = 0;
break;
}
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
switch (family) {
......
......@@ -101,19 +101,21 @@ static int r600_draw_common(struct r600_draw *draw)
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
if (vs_resource == NULL)
return -ENOMEM;
vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
S_038008_DATA_FORMAT(format);
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
r = radeon_draw_set_new(rctx->draw, vs_resource);
......@@ -121,22 +123,29 @@ static int r600_draw_common(struct r600_draw *draw)
return r;
}
/* FIXME start need to change winsys */
draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
if (draw->index_buffer) {
draw->draw = radeon_state(rscreen->rw, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
rbuffer = (struct r600_resource*)draw->index_buffer;
draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw->nbo = 1;
draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
} else {
draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
}
r = radeon_draw_set_new(rctx->draw, draw->draw);
if (r)
return r;
draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
draw->vgt = radeon_state(rscreen->rw, R600_VGT);
if (draw->vgt == NULL)
return -ENOMEM;
draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
......@@ -145,23 +154,18 @@ static int r600_draw_common(struct r600_draw *draw)
draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
r = radeon_draw_set_new(rctx->draw, draw->vgt);
if (r)
return r;
/* FIXME */
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
if (r == -EBUSY) {
r600_flush(draw->ctx, 0, NULL);
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
}
if (r)
return r;
rctx->draw = radeon_draw_duplicate(rctx->draw);
return 0;
}
......
......@@ -36,10 +36,11 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......@@ -55,10 +56,11 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
rstate = radeon_state(rscreen->rw, R600_QUERY_END);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......
......@@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
unsigned i, tmp;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
state = radeon_state(rscreen->rw, R600_VS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < 10; i++) {
......@@ -151,6 +151,8 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->nbo = 2;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
return radeon_state_pm4(state);
}
......@@ -165,7 +167,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rasterizer = &rctx->rasterizer->state.rasterizer;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
state = radeon_state(rscreen->rw, R600_PS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < rshader->ninput; i++) {
......@@ -204,6 +206,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
rpshader->rstate->nbo = 1;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
return radeon_state_pm4(state);
}
......
......@@ -283,19 +283,17 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_context *rctx = r600_context(ctx);
unsigned nconstant = 0, i, type, id;
unsigned nconstant = 0, i, id;
struct radeon_state *rstate;
struct pipe_transfer *transfer;
u32 *ptr;
switch (shader) {
case PIPE_SHADER_VERTEX:
id = R600_VS_CONSTANT;
type = R600_VS_CONSTANT_TYPE;
id = R600_VS_CONSTANT0;
break;
case PIPE_SHADER_FRAGMENT:
id = R600_PS_CONSTANT;
type = R600_PS_CONSTANT_TYPE;
id = R600_PS_CONSTANT0;
break;
default:
R600_ERR("unsupported %d\n", shader);
......@@ -307,7 +305,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
if (ptr == NULL)
return;
for (i = 0; i < nconstant; i++) {
rstate = radeon_state(rscreen->rw, type, id + i);
rstate = radeon_state(rscreen->rw, id + i);
if (rstate == NULL)
return;
rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
......@@ -622,7 +620,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
const struct pipe_blend_state *state = &rctx->blend->state.blend;
int i;
rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
rstate = radeon_state(rscreen->rw, R600_BLEND);
if (rstate == NULL)
return NULL;
rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
......@@ -681,14 +679,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
struct radeon_state *rstate;
const struct pipe_clip_state *state = &rctx->clip->state.clip;
rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
rstate = radeon_state(rscreen->rw, R600_UCP0 + clip);
if (rstate == NULL)
return NULL;
rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -711,7 +709,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
unsigned format, swap, ntype;
const struct util_format_description *desc;
rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
rstate = radeon_state(rscreen->rw, R600_CB0 + cb);
if (rstate == NULL)
return NULL;
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
......@@ -722,6 +720,9 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
rstate->nbo = 3;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
......@@ -740,14 +741,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
S_0280A0_SOURCE_FORMAT(1) |
S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000;
rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return NULL;
......@@ -768,7 +769,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
if (state->zsbuf == NULL)
return NULL;
rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
rstate = radeon_state(rscreen->rw, R600_DB);
if (rstate == NULL)
return NULL;
......@@ -782,6 +783,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
level = state->zsbuf->level;
pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
......@@ -844,7 +846,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
prov_vtx = 0;
rctx->flat_shade = state->flatshade;
rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
......@@ -925,7 +927,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
}
tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
rstate = radeon_state(rscreen->rw, R600_SCISSOR);
if (rstate == NULL)
return NULL;
rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
......@@ -960,7 +962,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
......@@ -993,7 +995,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
if (rctx->ps_shader == NULL) {
return NULL;
}
rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
rstate = radeon_state(rscreen->rw, R600_DSA);
if (rstate == NULL)
return NULL;
......@@ -1145,7 +1147,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
rstate = radeon_state(rscreen->rw, id);
if (rstate == NULL)
return NULL;
rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
......@@ -1246,7 +1248,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
R600_ERR("unknow format %d\n", view->texture->format);
return NULL;
}
rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
rstate = radeon_state(rscreen->rw, id);
if (rstate == NULL) {
return NULL;
}
......@@ -1268,34 +1270,36 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
pitch = (tmp->pitch[0] / tmp->bpt);
pitch = (pitch + 0x7) & ~0x7;
/* FIXME properly handle first level != 0 */
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
rstate->states[R600_RESOURCE__RESOURCE_WORD0] =
S_038000_DIM(r600_tex_dim(view->texture->target)) |
S_038000_TILE_MODE(array_mode) |
S_038000_TILE_TYPE(tile_type) |
S_038000_PITCH((pitch / 8) - 1) |
S_038000_TEX_WIDTH(view->texture->width0 - 1);
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
rstate->states[R600_RESOURCE__RESOURCE_WORD1] =
S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
S_038004_DATA_FORMAT(format);
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] =
word4 |
S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
S_038010_REQUEST_SIZE(1) |
S_038010_BASE_LEVEL(view->first_level);
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
rstate->states[R600_RESOURCE__RESOURCE_WORD5] =
S_038014_LAST_LEVEL(view->last_level) |
S_038014_BASE_ARRAY(0) |
S_038014_LAST_ARRAY(0);
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
rstate->states[R600_RESOURCE__RESOURCE_WORD6] =
S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -1342,7 +1346,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
target_mask |= (pbs->rt[0].colormask << (4 * i));
}
}
rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
......@@ -1419,7 +1423,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
if (rctx->ps_sampler[i]) {
rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
&rctx->ps_sampler[i]->state.sampler,