Commit ca9cf611 authored by Christian König's avatar Christian König
Browse files

radeonsi: move draw state into new handling



Split it out into si_state_draw.c
Signed-off-by: default avatarChristian König <deathsimple@vodafone.de>
parent 0d6b0b51
......@@ -12,4 +12,5 @@ C_SOURCES := \
r600_translate.c \
r600_state_common.c \
radeonsi_pm4.c \
si_state.c
si_state.c \
si_state_draw.c
......@@ -176,24 +176,6 @@ void *si_create_vertex_elements(struct pipe_context *ctx,
return v;
}
static void r600_update_alpha_ref(struct r600_context *rctx)
{
#if 0
unsigned alpha_ref;
struct r600_pipe_state rstate;
alpha_ref = rctx->alpha_ref;
rstate.nregs = 0;
if (rctx->export_16bpc)
alpha_ref &= ~0x1FFF;
r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
r600_context_pipe_state_set(rctx, &rstate);
rctx->alpha_ref_dirty = false;
#endif
}
struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
......@@ -259,245 +241,6 @@ void r600_set_so_targets(struct pipe_context *ctx,
rctx->streamout_append_bitmask = append_bitmask;
}
static void r600_vertex_buffer_update(struct r600_context *rctx)
{
struct pipe_context *ctx = &rctx->context;
struct r600_pipe_state *rstate = &rctx->vs_user_data;
struct r600_resource *rbuffer, *t_list_buffer;
struct pipe_vertex_buffer *vertex_buffer;
unsigned i, count, offset;
uint32_t *ptr;
uint64_t va;
r600_inval_vertex_cache(rctx);
/* bind vertex buffer once */
count = rctx->nr_vertex_buffers;
assert(count <= 256 / 4);
t_list_buffer = (struct r600_resource*)
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
PIPE_USAGE_IMMUTABLE, 4 * 4 * count);
if (t_list_buffer == NULL)
return;
ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->cs_buf,
rctx->cs,
PIPE_TRANSFER_WRITE);
for (i = 0 ; i < count; i++, ptr += 4) {
struct pipe_vertex_element *velem = &rctx->vertex_elements->elements[i];
const struct util_format_description *desc;
unsigned data_format, num_format;
int first_non_void;
/* bind vertex buffer once */
vertex_buffer = &rctx->vertex_buffer[i];
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = 0;
if (vertex_buffer == NULL || rbuffer == NULL)
continue;
offset += vertex_buffer->buffer_offset;
va = r600_resource_va(ctx->screen, (void*)rbuffer);
va += offset;
desc = util_format_description(velem->src_format);
first_non_void = util_format_get_first_non_void_channel(velem->src_format);
data_format = si_translate_vertexformat(ctx->screen,
velem->src_format,
desc, first_non_void);
switch (desc->channel[first_non_void].type) {
case UTIL_FORMAT_TYPE_FIXED:
num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
break;
case UTIL_FORMAT_TYPE_SIGNED:
num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
break;
case UTIL_FORMAT_TYPE_UNSIGNED:
num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
break;
case UTIL_FORMAT_TYPE_FLOAT:
default:
num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
}
/* Fill in T# buffer resource description */
ptr[0] = va & 0xFFFFFFFF;
ptr[1] = (S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(vertex_buffer->stride));
if (vertex_buffer->stride > 0)
ptr[2] = ((vertex_buffer->buffer->width0 - offset) /
vertex_buffer->stride);
else
ptr[2] = vertex_buffer->buffer->width0 - offset;
ptr[3] = (S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
S_008F0C_NUM_FORMAT(num_format) |
S_008F0C_DATA_FORMAT(data_format));
r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ);
}
rstate->nregs = 0;
va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
r600_pipe_state_add_reg(rstate,
R_00B148_SPI_SHADER_USER_DATA_VS_6,
va, t_list_buffer, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_00B14C_SPI_SHADER_USER_DATA_VS_7,
va >> 32,
NULL, 0);
r600_context_pipe_state_set(rctx, rstate);
}
static void si_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
if (!rctx->blitter->running) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
r600_flush_depth_textures(rctx);
}
if ((rctx->ps_shader->shader.fs_write_all &&
(rctx->ps_shader->shader.nr_cbufs != rctx->framebuffer.nr_cbufs)) ||
(rctx->sprite_coord_enable &&
(rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) {
si_pipe_shader_destroy(&rctx->context, rctx->ps_shader);
}
if (rctx->alpha_ref_dirty) {
r600_update_alpha_ref(rctx);
}
if (!rctx->vs_shader->bo) {
si_pipe_shader_vs(ctx, rctx->vs_shader);
}
if (!rctx->ps_shader->bo) {
si_pipe_shader_ps(ctx, rctx->ps_shader);
}
if (rctx->shader_dirty) {
si_update_spi_map(rctx);
rctx->shader_dirty = false;
}
}
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_state_dsa *dsa = rctx->queued.named.dsa;
struct pipe_draw_info info = *dinfo;
struct r600_draw rdraw = {};
struct pipe_index_buffer ib = {};
struct r600_block *dirty_block = NULL, *next_block = NULL;
struct r600_atom *state = NULL, *next_state = NULL;
int i;
if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
(info.indexed && !rctx->index_buffer.buffer)) {
return;
}
if (!rctx->ps_shader || !rctx->vs_shader)
return;
si_update_derived_state(rctx);
r600_vertex_buffer_update(rctx);
rdraw.vgt_num_indices = info.count;
rdraw.vgt_num_instances = info.instance_count;
if (info.indexed) {
/* Initialize the index buffer struct. */
pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
ib.index_size = rctx->index_buffer.index_size;
ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info.count);
if (ib.user_buffer) {
r600_upload_index_buffer(rctx, &ib, info.count);
}
/* Initialize the r600_draw struct with index buffer info. */
if (ib.index_size == 4) {
rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
(R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
} else {
rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
(R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
}
rdraw.indices = (struct r600_resource*)ib.buffer;
rdraw.indices_bo_offset = ib.offset;
rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
} else {
info.index_bias = info.start;
rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
if (info.count_from_stream_output) {
rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
}
}
rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
if (!si_update_draw_info_state(rctx, &info))
return;
rdraw.db_render_override = dsa->db_render_override;
rdraw.db_render_control = dsa->db_render_control;
/* Emit states. */
rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
r600_need_cs_space(rctx, 0, TRUE);
LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
r600_emit_atom(rctx, state);
}
LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
r600_context_block_emit_dirty(rctx, dirty_block);
}
si_pm4_emit_dirty(rctx);
rctx->pm4_dirty_cdwords = 0;
/* Enable stream out if needed. */
if (rctx->streamout_start) {
r600_context_streamout_begin(rctx);
rctx->streamout_start = FALSE;
}
for (i = 0; i < NUM_TEX_UNITS; i++) {
if (rctx->ps_samplers.views[i])
r600_context_bo_reloc(rctx,
(struct r600_resource*)rctx->ps_samplers.views[i]->base.texture,
RADEON_USAGE_READ);
}
si_context_draw(rctx, &rdraw);
rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
if (rctx->framebuffer.zsbuf)
{
struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
((struct r600_resource_texture *)tex)->dirty_db = TRUE;
}
pipe_resource_reference(&ib.buffer, NULL);
}
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
......
......@@ -213,7 +213,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
r600_init_surface_functions(rctx);
rctx->context.draw_vbo = r600_draw_vbo;
rctx->context.create_video_decoder = vl_create_decoder;
rctx->context.create_video_buffer = vl_video_buffer_create;
......
......@@ -163,9 +163,8 @@ struct r600_context {
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
struct r600_pipe_state config;
struct si_pipe_shader *ps_shader;
struct si_pipe_shader *vs_shader;
struct r600_pipe_state vs_user_data;
struct si_pipe_shader *ps_shader;
struct si_pipe_shader *vs_shader;
struct pipe_query *current_render_cond;
unsigned current_render_cond_mode;
struct pipe_query *saved_render_cond;
......@@ -253,8 +252,6 @@ static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *
/* evergreen_state.c */
void cayman_init_state_functions(struct r600_context *rctx);
void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
uint32_t si_translate_vertexformat(struct pipe_screen *screen,
enum pipe_format format,
const struct util_format_description *desc,
......@@ -339,7 +336,6 @@ void r600_set_so_targets(struct pipe_context *ctx,
unsigned num_targets,
struct pipe_stream_output_target **targets,
unsigned append_bitmask);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
/*
* common helpers
......
......@@ -26,6 +26,7 @@
#include "util/u_memory.h"
#include "util/u_framebuffer.h"
#include "util/u_blitter.h"
#include "tgsi/tgsi_parse.h"
#include "radeonsi_pipe.h"
#include "si_state.h"
......@@ -1362,173 +1363,6 @@ static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
free(shader);
}
void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
unsigned num_sgprs, num_user_sgprs;
unsigned nparams, i;
uint64_t va;
if (si_pipe_shader_create(ctx, shader))
return;
si_pm4_delete_state(rctx, vs, shader->pm4);
pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
si_pm4_inval_shader_cache(pm4);
/* Certain attributes (position, psize, etc.) don't count as params.
* VS is required to export at least one param and r600_shader_from_tgsi()
* takes care of adding a dummy export.
*/
for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
nparams++;
}
if (nparams < 1)
nparams = 1;
si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
S_0286C4_VS_EXPORT_COUNT(nparams - 1));
si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
va = r600_resource_va(ctx->screen, (void *)shader->bo);
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
num_user_sgprs = 8;
num_sgprs = shader->num_sgprs;
if (num_user_sgprs > num_sgprs)
num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs += 2;
assert(num_sgprs <= 104);
si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
S_00B128_SGPRS((num_sgprs - 1) / 8));
si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
S_00B12C_USER_SGPR(num_user_sgprs));
si_pm4_bind_state(rctx, vs, shader->pm4);
}
void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
unsigned spi_baryc_cntl;
uint64_t va;
if (si_pipe_shader_create(ctx, shader))
return;
si_pm4_delete_state(rctx, ps, shader->pm4);
pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
si_pm4_inval_shader_cache(pm4);
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i < shader->shader.ninput; i++) {
ninterp++;
/* XXX: Flat shading hangs the GPU */
if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
(shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
rctx->queued.named.rasterizer->flatshade))
have_linear = TRUE;
if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
have_linear = TRUE;
if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
have_perspective = TRUE;
if (shader->shader.input[i].centroid)
have_centroid = TRUE;
}
for (i = 0; i < shader->shader.noutput; i++) {
if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
}
if (shader->shader.uses_kill)
db_shader_control |= S_02880C_KILL_ENABLE(1);
exports_ps = 0;
num_cout = 0;
for (i = 0; i < shader->shader.noutput; i++) {
if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
exports_ps |= 1;
else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
if (shader->shader.fs_write_all)
num_cout = shader->shader.nr_cbufs;
else
num_cout++;
}
}
if (!exports_ps) {
/* always at least export 1 component per pixel */
exports_ps = 2;
}
spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
spi_baryc_cntl = 0;
if (have_perspective)
spi_baryc_cntl |= have_centroid ?
S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
if (have_linear)
spi_baryc_cntl |= have_centroid ?
S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, shader->spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, shader->spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
/* XXX: Depends on Z buffer format? */
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
/* XXX: Depends on color buffer format? */
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR));
va = r600_resource_va(ctx->screen, (void *)shader->bo);
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
num_user_sgprs = 6;
num_sgprs = shader->num_sgprs;
if (num_user_sgprs > num_sgprs)
num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs += 2;
assert(num_sgprs <= 104);
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
S_00B028_SGPRS((num_sgprs - 1) / 8));
si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
S_00B02C_USER_SGPR(num_user_sgprs));
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
shader->sprite_coord_enable = rctx->sprite_coord_enable;
si_pm4_bind_state(rctx, ps, shader->pm4);
}
/*
* Samplers
*/
......@@ -1562,12 +1396,16 @@ static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
pipe_sampler_view_reference(
(struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
views[i]);
si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
if (resource[i]) {
if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
if (tex->depth)
has_depth = 1;
memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
......@@ -1726,6 +1564,8 @@ void si_init_state_functions(struct r600_context *rctx)
rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
rctx->context.set_constant_buffer = si_set_constant_buffer;
rctx->context.draw_vbo = si_draw_vbo;
}
void si_init_config(struct r600_context *rctx)
......@@ -1767,125 +1607,3 @@ void si_init_config(struct r600_context *rctx)
si_pm4_set_state(rctx, init, pm4);
}
static unsigned si_conv_pipe_prim(unsigned pprim)
{
static const unsigned prim_conv[] = {
[PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
[PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
[PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
[PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
[PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
[PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
[PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
[PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
[PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
[PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
[PIPE_PRIM_LINES_ADJACENCY] = ~0,
[PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
[PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
};
unsigned result = prim_conv[pprim];
if (result == ~0) {
R600_ERR("unsupported primitive type %d\n", pprim);
}
return result;
}
bool si_update_draw_info_state(struct r600_context *rctx,
const struct pipe_draw_info *info)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
unsigned prim = si_conv_pipe_prim(info->mode);
unsigned ls_mask = 0;
if (pm4 == NULL)
return false;
if (prim == ~0) {
FREE(pm4);
return false;
}
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
#if 0
si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
#endif
if (prim == V_008958_DI_PT_LINELIST)
ls_mask = 1;
else if (prim == V_008958_DI_PT_LINESTRIP)
ls_mask = 2;
si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
S_028A0C_AUTO_RESET_CNTL(ls_mask) |
rctx->pa_sc_line_stipple);
if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
} else {
si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
}
si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,