Commit d3cd6b72 authored by Francisco Jerez's avatar Francisco Jerez Committed by Jason Ekstrand
Browse files

intel/fs: Replace the CINTERP opcode with a simple MOV



The only reason it was it's own opcode was so that we could detect it
and adjust the source register based on the payload setup.  Now that
we're using the ATTR file for FS inputs, there's no point in having a
magic opcode for this.

v2 (Jason Ekstrand):
 - Break the bit which removes the CINTERP opcode into its own patch
Reviewed-by: default avatarJason Ekstrand <jason@jlekstrand.net>
Reviewed-by: default avatarMatt Turner <mattst88@gmail.com>
parent 39de901a
...@@ -499,7 +499,6 @@ enum opcode { ...@@ -499,7 +499,6 @@ enum opcode {
*/ */
FS_OPCODE_DDY_COARSE, FS_OPCODE_DDY_COARSE,
FS_OPCODE_DDY_FINE, FS_OPCODE_DDY_FINE,
FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP, FS_OPCODE_LINTERP,
FS_OPCODE_PIXEL_X, FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y, FS_OPCODE_PIXEL_Y,
......
...@@ -75,7 +75,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst) ...@@ -75,7 +75,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7: case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP: case FS_OPCODE_LINTERP:
case SHADER_OPCODE_FIND_LIVE_CHANNEL: case SHADER_OPCODE_FIND_LIVE_CHANNEL:
case SHADER_OPCODE_BROADCAST: case SHADER_OPCODE_BROADCAST:
......
...@@ -2112,9 +2112,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) ...@@ -2112,9 +2112,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
BRW_MATH_PRECISION_FULL); BRW_MATH_PRECISION_FULL);
} }
break; break;
case FS_OPCODE_CINTERP:
brw_MOV(p, dst, src[0]);
break;
case FS_OPCODE_LINTERP: case FS_OPCODE_LINTERP:
multiple_instructions_emitted = generate_linterp(inst, dst, src); multiple_instructions_emitted = generate_linterp(inst, dst, src);
break; break;
......
...@@ -3392,8 +3392,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, ...@@ -3392,8 +3392,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
} }
for (unsigned int i = 0; i < num_components; i++) { for (unsigned int i = 0; i < num_components; i++) {
bld.emit(FS_OPCODE_CINTERP, offset(retype(dest, type), bld, i), bld.MOV(offset(retype(dest, type), bld, i),
retype(component(interp_reg(base, comp + i), 3), type)); retype(component(interp_reg(base, comp + i), 3), type));
} }
if (nir_dest_bit_size(instr->dest) == 64) { if (nir_dest_bit_size(instr->dest) == 64) {
......
...@@ -378,8 +378,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) ...@@ -378,8 +378,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case FS_OPCODE_DDY_FINE: case FS_OPCODE_DDY_FINE:
return "ddy_fine"; return "ddy_fine";
case FS_OPCODE_CINTERP:
return "cinterp";
case FS_OPCODE_LINTERP: case FS_OPCODE_LINTERP:
return "linterp"; return "linterp";
...@@ -960,7 +958,6 @@ backend_instruction::can_do_cmod() const ...@@ -960,7 +958,6 @@ backend_instruction::can_do_cmod() const
case BRW_OPCODE_SHR: case BRW_OPCODE_SHR:
case BRW_OPCODE_SUBB: case BRW_OPCODE_SUBB:
case BRW_OPCODE_XOR: case BRW_OPCODE_XOR:
case FS_OPCODE_CINTERP:
case FS_OPCODE_LINTERP: case FS_OPCODE_LINTERP:
return true; return true;
default: default:
...@@ -987,8 +984,7 @@ backend_instruction::writes_accumulator_implicitly(const struct gen_device_info ...@@ -987,8 +984,7 @@ backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
return writes_accumulator || return writes_accumulator ||
(devinfo->gen < 6 && (devinfo->gen < 6 &&
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) || ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP && (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP)));
opcode != FS_OPCODE_CINTERP)));
} }
bool bool
......
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