1. 30 May, 2018 3 commits
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  6. 05 Mar, 2018 1 commit
    • gurchetansingh@chromium.org's avatar
      virgl: add offset alignment values to to v2 caps struct · fe0647df
      gurchetansingh@chromium.org authored
      
      
      glBindBufferRange(..) in vrend_draw_bind_ubo is failing with
      more than one uniform block. This is due to improper alignment
      of the start of the second block. Let's query the proper
      alignment from the driver and pass it back to Mesa.
      
      Let's query for the texture alignment too, even though the Virgl
      renderer doesn't call glTexBufferRange yet.
      
      The default values are the widest workable range possible (for example,
      GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT on Nvidia is 256).
      
      Fixes:
      	dEQP-GLES3.functional.ubo.* on Nvidia
      
      Example test:
      	dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.shared_vertex
      
      Note: This is based on "virgl: reduce some default capset limits.",
      which hasn't landed in Mesa yet but should relatively soon.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      fe0647df
  7. 17 Feb, 2018 1 commit
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  10. 30 Jan, 2018 1 commit
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  12. 19 Dec, 2017 1 commit
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  14. 06 Nov, 2017 1 commit
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  16. 10 Oct, 2017 1 commit
    • Eric Anholt's avatar
      gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4. · ac0051a5
      Eric Anholt authored
      Because vc4 can control the order that tiles are rasterized in, we can use
      it to implement overlapping blits using normal drawing and
      GL_ARB_texture_barrier, as long as we can tell the kernel what order to
      render the tiles in.
      
      This commit introduces the core gallium support, vc4 changes will follow.
      
      v2: Fix on the simulator.
      v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
      v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
      v5: Drop vc4 changes from this commit, for clarity.
      
      Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
      ac0051a5
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