1. 29 May, 2018 1 commit
  2. 16 May, 2018 2 commits
  3. 25 Apr, 2018 1 commit
  4. 24 Apr, 2018 2 commits
  5. 12 Apr, 2018 1 commit
    • Eric Anholt's avatar
      broadcom/vc5: Fix MSAA depth/stencil size setup. · 7553cbfc
      Eric Anholt authored
      The v3dX(get_internal_type_bpp_for_output_format)() call only handles
      color output formats (which overlap in enum numbers with depth output
      formats), so for depth we just need to take the normal cpp times the
      number of samples.
      7553cbfc
  6. 28 Mar, 2018 1 commit
    • Eric Anholt's avatar
      broadcom/vc5: Fix padding of NPOT miplevels >= 2. · a691fa4a
      Eric Anholt authored
      The power-of-two padded size that gets minified is based on level 1's
      dimensions, not level 0's, which starts to differ at a width of 9.
      
      Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1
      a691fa4a
  7. 09 Mar, 2018 2 commits
  8. 28 Feb, 2018 1 commit
  9. 23 Feb, 2018 1 commit
    • Eric Anholt's avatar
      broadcom/vc5: Fix layout of 3D textures. · b4b4ada7
      Eric Anholt authored
      Cube maps are entire miptrees repeated, while 3D textures have each level
      have all of its layers next to each other.  Fixes tex3d and
      tex-miplevel-selection GL2:texture() 3D.
      b4b4ada7
  10. 03 Feb, 2018 2 commits
    • Eric Anholt's avatar
      broadcom/vc5: Enable UIF XOR on textures. · 2e746bc6
      Eric Anholt authored
      This should increase performance by reducing SDRAM bank conflicts when
      crossing between UIF columns (particularly on power-of-two height
      textures).
      
      The uif_xor_disable setup is dropped, since we need to allow XOR on lower
      miplevels even when level 0 is XOR.  The level 0 force UIF and level 0 XOR
      flags should handle setting XOR properly on imported buffers.
      2e746bc6
    • Eric Anholt's avatar
      broadcom/vc5: Fix alignment of miplevel 1 with UIF. · 6a862b0d
      Eric Anholt authored
      The alignment here means that we can't get back the padded height from the
      size/stride any more, so it's now a field in the slice as well.
      
      Fixes piglit fbo-generatemipmap-formats RGBA16 NPOT.
      6a862b0d
  11. 01 Feb, 2018 3 commits
    • Eric Anholt's avatar
      broadcom/vc5: Fix image_h setup for both loads and stores. · 06858c73
      Eric Anholt authored
      The image_h for the tiling algorithm needs to be the padded-to-a-uifblock
      height of the level, not the unpadded height or the height of level 0.
      Fixes some cases of KHR-GLES3.texture_repeat_mode.* and
      depthstencil-render-miplevels.
      06858c73
    • Eric Anholt's avatar
      broadcom/vc5: Add appropriate height padding for bank conflicts. · 5329f35e
      Eric Anholt authored
      I thought I didn't need this because I was doing level-0-always-UIF and
      that the pad there would propagate down, but it turns out that for level 1
      the padding ends up being chosen by the HW.  This brings us closer to
      being able to turn on UIF XOR for increased performance, as well.
      5329f35e
    • Eric Anholt's avatar
      broadcom/vc5: Simplify separate stencil surface setup. · dea902c9
      Eric Anholt authored
      If we just make another gallium surface for the separate stencil, it's a
      lot easier to keep track of which set of fields we're using in RCL setup.
      
      This also incidentally fixes a little bug in setting up the surface's
      padded height for separate stencil when the UIF-ness changes at different
      levels of Z versus stencil.
      dea902c9
  12. 13 Jan, 2018 1 commit
  13. 03 Jan, 2018 3 commits
  14. 19 Dec, 2017 3 commits
  15. 20 Nov, 2017 1 commit
  16. 18 Nov, 2017 1 commit
  17. 07 Nov, 2017 2 commits
  18. 30 Oct, 2017 4 commits
  19. 12 Oct, 2017 1 commit
  20. 10 Oct, 2017 1 commit
    • Eric Anholt's avatar
      broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268. · 45bb8f29
      Eric Anholt authored
      V3D 3.3 is a continuation of the 3D implementation in VC4 (v2.1 and v2.6).
      V3D 3.3 introduces an MMU (no more CMA allocations) and support for
      GLES3.1.  This driver is not currently conformant, though that will be a
      target as soon as possible.
      
      V3D 3.x parts use a new texture tiling layout common across many Broadcom
      graphics parts including and the HVS scanout engine.  It also massively
      changes the QPU instructions, introducing a common physical register file
      (no more A/B split) and half-float instructions, while removing the 4x8
      unorm instructions in favor of half-float for talking to fixed function
      interfaces.  Because so much has changed, vc5 is implemented in a separate
      gallium driver, using only the XML code-generation support from vc4.
      
      v2: Fix tile layout for 64bpp textures.  Fix texture swizzling for 32-bit
          returns.  Fix up a bit of MRT setup.  Sync the simulator to kernel
          behavior a bit more.  Improve uniform debugging code.  Rebase on
          QIR->VIR rename.  Move texture state mostly to the CSOs.  Improve
          cache flushing on the simulator.  Fix program deletion
          use-after-frees.
      
      Acked-by: Dave Airlie <airlied@gmail.com> (uabi plan)
      Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (uabi plan)
      45bb8f29