1. 26 Oct, 2018 1 commit
    • Rob Clark's avatar
      freedreno: import libdrm_freedreno + redesign submit · f3cc0d27
      Rob Clark authored
      In the pursuit of lowering driver overhead, it became clear that some
      amount of redesign of how libdrm_freedreno constructs the submit ioctl
      would be needed.  In particular, as the gallium driver is starting to
      make heavier use of CP_SET_DRAW_STATE state groups/objects, the over-
      head of tracking cmd buffers and relocs becomes too much.  And for
      "streaming" state, which isn't ever reused (like uniform uploads) the
      overhead of allocating/freeing ringbuffer[1] objects is too high.
      This redesign makes two main changes:
       1) Introduces a fd_submit object for tracking bos and cmds table
          for the submit ioctl, making ringbuffer objects more light-
          weight.  This was previously done in the ringbuffer.  But we
          have many ringbuffer instances involved in a submit (gmem +
          draw + potentially 1000's of state-group rbs), and only need
          a single bos and cmds table.  (Reloc table is still per-rb)
          The submit is also a convenient place for a slab allocator for
          ringbuffer objects.  Other options would have required locking
          because, while we can guarantee allocations will only happen on
          a single thread, free's could happen either on the application
          thread or the flush_queue thread.  With the slab allocator in
          the submit object, any frees that happen on the flush_queue
          thread happen after we know that the application thread is done
          with the submit.
       2) Introduce a new "softpin" msm_ringbuffer_sp implementation that
          does not use relocs and only has cmds table entries for IB1 (ie.
          the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER
          to from the RB).  To do this properly will require some updates
          on the kernel side, so whether you get the softpin or legacy
          submit/ringbuffer implementation at runtime depends on your
          kernel version.
      To make all these changes in libdrm would basically require adding a
      libdrm_freedreno2, so this is a good point to just pull the libdrm code
      into mesa.  Plus it allows for using mesa's hashtable, slab allocator,
      etc.  And it lets us have asserts enabled for debug mesa buids but
      omitted for release builds.  And it makes life easier if further API
      changes become necessary.
      At this point I haven't tried to pull in the kgsl backend.  Although
      I left the level of vfunc indirection which would make it possible
      to have other backends.  (And this was convenient to keep to allow
      for the "softpin" ringbuffer to coexist.)
      NOTE: if bisecting a build error takes you here, try a clean build.
      There are a bunch of ways things can go wrong if you still have
      libdrm_freedreno cflags.
      [1] "ringbuffer" is probably a bad name, the only level of cmdstream
          buffer that is actually a ring is RB managed by kernel.  User-
          space cmdstream is all IB1/IB2 and state-groups.
      Reviewed-by: default avatarKristian H. Kristensen <hoegsberg@chromium.org>
      Reviewed-by: default avatarEric Engestrom <eric.engestrom@intel.com>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
  2. 24 Aug, 2018 1 commit
  3. 23 Aug, 2018 1 commit
  4. 16 Aug, 2018 1 commit
  5. 25 Jan, 2018 1 commit
  6. 20 Jan, 2018 1 commit
  7. 24 Oct, 2017 1 commit
  8. 27 Jan, 2017 1 commit
  9. 30 Nov, 2016 1 commit
  10. 30 May, 2016 1 commit
  11. 25 May, 2016 1 commit
  12. 25 Apr, 2016 1 commit
    • Rob Clark's avatar
      freedreno/ir3: fix sin/cos · 4610e5ef
      Rob Clark authored
      We seem to need range reduction to get sane results.  Fixes glmark2
      jellyfish bench, and a whole bunch of
      v2: squashed in android build fixes from Rob Herring
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
  13. 26 Jan, 2016 1 commit
  14. 16 Oct, 2015 1 commit
  15. 26 Jun, 2015 1 commit
  16. 12 Jun, 2015 2 commits
  17. 05 Apr, 2015 1 commit
  18. 12 Dec, 2014 1 commit
  19. 15 Nov, 2014 1 commit
  20. 16 Sep, 2014 1 commit
  21. 05 Sep, 2014 1 commit
  22. 12 Aug, 2014 1 commit
  23. 25 Jul, 2014 1 commit
    • Rob Clark's avatar
      freedreno/ir3: split out shader compiler from a3xx · db193e5a
      Rob Clark authored
      Move the bits we want to share between generations from fd3_program to
      ir3_shader.  So overall structure is:
        fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3
                                          |- ...
                                          \- ir3_shader_variant -> ir3
      So the ir3_shader becomes the topmost generation neutral object, which
      manages the set of variants each of which generates, compiles, and
      assembles it's own ir.
      There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/,
      Keep the split between the gallium level stateobj and the shader helper
      object because it might be a good idea to pre-compute some generation
      specific register values (ie. anything that is independent of linking).
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
  24. 16 Nov, 2013 3 commits
  25. 01 Oct, 2013 1 commit
  26. 08 Jun, 2013 2 commits
    • Rob Clark's avatar
      freedreno: add a3xx support · 2855f3f7
      Rob Clark authored
      The adreno a3xx GPU is found in newer snapdragon devices, such as the
      nexus4.  The a3xx is GLESv3 and OpenCL capable, although that is not
      enabled yet in gallium.
      Compared to a2xx, it introduces an entirely new unified shader ISA, and
      re-shuffles all or nearly all of the registers.  The good news is that
      (for the most part) the registers are more orthogonal, not combining
      unrelated state in a single register.  And that there is a lot more
      flexibility, so we don't need to patch and re-emit the shader like we
      did on a2xx.
      The shader compiler is currently quite dumb, there would be a lot of
      room for improvement with an optimizing pass.  Despite that, with the
      a320 in my nexus4 it seems to be ~2-3x faster compared to the a220 in my
      HP touchpad.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
    • Rob Clark's avatar
      freedreno: prepare for a3xx · 18c317b2
      Rob Clark authored
      Split the parts that are specific to adreno a2xx series GPUs from the
      parts that will be in common with a3xx, so that a3xx support can be
      added more cleanly.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
  27. 20 Apr, 2013 1 commit
    • Rob Clark's avatar
      freedreno: move ir -> ir2 · 26b39df0
      Rob Clark authored
      There will be a new IR for a3xx, which has a very different shader ISA
      (more scalar oriented).  So rename to avoid conflicts later when I start
      adding a3xx support to the gallium driver.
      Signed-off-by: Rob Clark <Rob Clark robdclark@freedesktop.org>
  28. 12 Mar, 2013 1 commit
    • Rob Clark's avatar
      freedreno: gallium driver for adreno · 6173cc19
      Rob Clark authored
      Currently works on a220.  Others in the a2xx family look pretty similar
      and should be pretty straightforward to support with the same driver.
      The a3xx has a new shader ISA, and while many registers appear similar,
      the register addresses have been completely shuffled around.  I am not
      sure yet whether it is best to support with the same driver, but
      different compiler, or whether it should be split into a different
      v1: original
      v2: build file updates from review comments, and remove GPL licensed
          header files from msm kernel
      v3: smarter temp/pred register assignment, fix clear and depth/stencil
          format issues, resource_transfer fixes, scissor fixes
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>