1. 26 Oct, 2018 1 commit
    • Rob Clark's avatar
      freedreno: import libdrm_freedreno + redesign submit · f3cc0d27
      Rob Clark authored
      In the pursuit of lowering driver overhead, it became clear that some
      amount of redesign of how libdrm_freedreno constructs the submit ioctl
      would be needed.  In particular, as the gallium driver is starting to
      make heavier use of CP_SET_DRAW_STATE state groups/objects, the over-
      head of tracking cmd buffers and relocs becomes too much.  And for
      "streaming" state, which isn't ever reused (like uniform uploads) the
      overhead of allocating/freeing ringbuffer[1] objects is too high.
      
      This redesign makes two main changes:
      
       1) Introduces a fd_submit object for tracking bos and cmds table
          for the submit ioctl, making ringbuffer objects more light-
          weight.  This was previously done in the ringbuffer.  But we
          have many ringbuffer instances involved in a submit (gmem +
          draw + potentially 1000's of state-group rbs), and only need
          a single bos and cmds table.  (Reloc table is still per-rb)
      
          The submit is also a convenient place for a slab allocator for
          ringbuffer objects.  Other options would have required locking
          because, while we can guarantee allocations will only happen on
          a single thread, free's could happen either on the application
          thread or the flush_queue thread.  With the slab allocator in
          the submit object, any frees that happen on the flush_queue
          thread happen after we know that the application thread is done
          with the submit.
      
       2) Introduce a new "softpin" msm_ringbuffer_sp implementation that
          does not use relocs and only has cmds table entries for IB1 (ie.
          the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER
          to from the RB).  To do this properly will require some updates
          on the kernel side, so whether you get the softpin or legacy
          submit/ringbuffer implementation at runtime depends on your
          kernel version.
      
      To make all these changes in libdrm would basically require adding a
      libdrm_freedreno2, so this is a good point to just pull the libdrm code
      into mesa.  Plus it allows for using mesa's hashtable, slab allocator,
      etc.  And it lets us have asserts enabled for debug mesa buids but
      omitted for release builds.  And it makes life easier if further API
      changes become necessary.
      
      At this point I haven't tried to pull in the kgsl backend.  Although
      I left the level of vfunc indirection which would make it possible
      to have other backends.  (And this was convenient to keep to allow
      for the "softpin" ringbuffer to coexist.)
      
      NOTE: if bisecting a build error takes you here, try a clean build.
      There are a bunch of ways things can go wrong if you still have
      libdrm_freedreno cflags.
      
      [1] "ringbuffer" is probably a bad name, the only level of cmdstream
          buffer that is actually a ring is RB managed by kernel.  User-
          space cmdstream is all IB1/IB2 and state-groups.
      Reviewed-by: default avatarKristian H. Kristensen <hoegsberg@chromium.org>
      Reviewed-by: default avatarEric Engestrom <eric.engestrom@intel.com>
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      f3cc0d27
  2. 17 Oct, 2018 2 commits
    • Rob Clark's avatar
      freedreno/a6xx: use program cache · b4e94af3
      Rob Clark authored
      Use the in-memory cache to construct shader program state and re-use it
      on subsequent draws, to lower driver overhead.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      b4e94af3
    • Rob Clark's avatar
      freedreno/a6xx: texture state obj · 1b9d6941
      Rob Clark authored
      Unfortunately gallium doesn't match what the hw wants perfectly here, in
      using a separate CSO for each texture/sampler.  So we have to use a hash
      table to map the collection of texture/samplers to hw state object.
      
      We probably could use separate hw state objects for texture and sampler
      state, but mesa/st tends to update the tex and samp state together.
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      1b9d6941
  3. 08 Oct, 2018 2 commits
  4. 02 Oct, 2018 1 commit
  5. 17 Aug, 2018 1 commit
  6. 16 Aug, 2018 1 commit
  7. 14 Nov, 2017 1 commit
  8. 12 Nov, 2017 1 commit
  9. 23 May, 2017 1 commit
  10. 22 Apr, 2017 1 commit
  11. 18 Dec, 2016 1 commit
  12. 30 Nov, 2016 1 commit
  13. 13 Aug, 2016 1 commit
  14. 24 Apr, 2016 2 commits
  15. 19 Apr, 2016 1 commit
    • Rob Clark's avatar
      freedreno/a4xx: lower srgb in shader for astc textures · 899bd63a
      Rob Clark authored
      This *seems* like a hw bug, and maybe only applies to certain a4xx
      variants/revisions.  But setting the SRGB bit in sampler view state
      (texconst0) causes invalid alpha for ASTC textures.  Work around this
      by doing the srgb->linear conversion in the shader instead.
      
      This fixes 392 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
      
      (The remaining fails seem to be a bug w/ ASTC + linear filtering, also
      possibly a420.0 specific.)
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      899bd63a
  16. 13 Mar, 2016 1 commit
  17. 17 Feb, 2016 1 commit
  18. 15 Sep, 2015 1 commit
  19. 26 Aug, 2015 1 commit
  20. 21 Jul, 2015 1 commit
    • Ilia Mirkin's avatar
      gallium: replace INLINE with inline · a2a1a580
      Ilia Mirkin authored
      Generated by running:
      git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g'
      git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g'
      git checkout src/gallium/state_trackers/clover/Doxyfile
      
      and manual edits to
      src/gallium/include/pipe/p_compiler.h
      src/gallium/README.portability
      
      to remove mentions of the inline define.
      Signed-off-by: default avatarIlia Mirkin <imirkin@alum.mit.edu>
      Acked-by: default avatarMarek Olšák <marek.olsak@amd.com>
      a2a1a580
  21. 21 Jun, 2015 1 commit
  22. 22 Apr, 2015 1 commit
  23. 15 Nov, 2014 1 commit
  24. 15 Oct, 2014 2 commits
  25. 29 Sep, 2014 2 commits
  26. 24 Sep, 2014 1 commit
    • Rob Clark's avatar
      freedreno/a3xx: initial texture border-color · a87e44da
      Rob Clark authored
      Still some open questions.. and at any rate, no additional piglit passes
      due to various wrap modes that we need to emulate in at least some
      cases :-(
      
      But it does fix some mystery page-faults.. So add some comments in the
      code where there are things that we need to emulate or do more r/e, and
      push as-is.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      a87e44da
  27. 08 Jan, 2014 1 commit
  28. 26 Dec, 2013 1 commit
    • Rob Clark's avatar
      freedreno: prepare for hw binning · be01d7a9
      Rob Clark authored
      Actually assign VSC_PIPE's properly, which will be needed for tiling.
      And introduce fd_tile for per-tile state (including the assignment of
      tile to VSC_PIPE).  This gives us the proper pipe setup that we'll
      need for hw binning pass, and also cleans things up a bit by not having
      to pass so many parameters around.  And will also make it easier to
      introduce different tiling patterns (since we may no longer render
      tiles in a simple left-to-right top-to-bottom pattern).
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      be01d7a9
  29. 08 Jun, 2013 2 commits
    • Rob Clark's avatar
      freedreno: add a3xx support · 2855f3f7
      Rob Clark authored
      The adreno a3xx GPU is found in newer snapdragon devices, such as the
      nexus4.  The a3xx is GLESv3 and OpenCL capable, although that is not
      enabled yet in gallium.
      
      Compared to a2xx, it introduces an entirely new unified shader ISA, and
      re-shuffles all or nearly all of the registers.  The good news is that
      (for the most part) the registers are more orthogonal, not combining
      unrelated state in a single register.  And that there is a lot more
      flexibility, so we don't need to patch and re-emit the shader like we
      did on a2xx.
      
      The shader compiler is currently quite dumb, there would be a lot of
      room for improvement with an optimizing pass.  Despite that, with the
      a320 in my nexus4 it seems to be ~2-3x faster compared to the a220 in my
      HP touchpad.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      2855f3f7
    • Rob Clark's avatar
      freedreno: prepare for a3xx · 18c317b2
      Rob Clark authored
      Split the parts that are specific to adreno a2xx series GPUs from the
      parts that will be in common with a3xx, so that a3xx support can be
      added more cleanly.
      Signed-off-by: default avatarRob Clark <robclark@freedesktop.org>
      18c317b2
  30. 12 Mar, 2013 1 commit
    • Rob Clark's avatar
      freedreno: gallium driver for adreno · 6173cc19
      Rob Clark authored
      Currently works on a220.  Others in the a2xx family look pretty similar
      and should be pretty straightforward to support with the same driver.
      
      The a3xx has a new shader ISA, and while many registers appear similar,
      the register addresses have been completely shuffled around.  I am not
      sure yet whether it is best to support with the same driver, but
      different compiler, or whether it should be split into a different
      driver.
      
      v1: original
      v2: build file updates from review comments, and remove GPL licensed
          header files from msm kernel
      v3: smarter temp/pred register assignment, fix clear and depth/stencil
          format issues, resource_transfer fixes, scissor fixes
      Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
      6173cc19
  31. 07 Mar, 2013 1 commit
  32. 23 Apr, 2012 1 commit
  33. 02 Dec, 2011 1 commit
  34. 13 Oct, 2010 1 commit