• Ilia Mirkin's avatar
    nv50/ir/ra: enforce max register requirement, and change spill order · beb66d37
    Ilia Mirkin authored
    On nv50, certain operations must happen on regs below 64, due to
    encoding requirements. First of all, we add infrastructure to enforce
    this. Secondly we change the spill order to first spill RIG nodes that
    are unconstrained, followed by ones that are.
    
    This makes the gamecube logo shadertoy compile properly. Curiously, if
    we adjust the spill order so that we first spill the constrained RIG
    nodes instead, the RA also succeeds. However it seems more logical to
    first spill the unconstrained ones.
    
    While we're at it, drop the nv50 max register to reserve r127 as the
    zero register of last resort (r63 is preferred).
    Signed-off-by: 's avatarIlia Mirkin <imirkin@alum.mit.edu>
    Acked-by: 's avatarKarol Herbst <kherbst@redhat.com>
    beb66d37
nv50_ir_ra.cpp 71.8 KB