Commit 461a8643 authored by Marek Olšák's avatar Marek Olšák

winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

parent 0f79b201
......@@ -74,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
# in the first entry.
LIBDRM_REQUIRED=2.4.75
LIBDRM_RADEON_REQUIRED=2.4.71
LIBDRM_AMDGPU_REQUIRED=2.4.91
LIBDRM_AMDGPU_REQUIRED=2.4.93
LIBDRM_INTEL_REQUIRED=2.4.75
LIBDRM_NVVIEUX_REQUIRED=2.4.66
LIBDRM_NOUVEAU_REQUIRED=2.4.66
......
......@@ -1080,7 +1080,7 @@ dep_libdrm_etnaviv = null_dep
dep_libdrm_freedreno = null_dep
dep_libdrm_intel = null_dep
_drm_amdgpu_ver = '2.4.91'
_drm_amdgpu_ver = '2.4.93'
_drm_radeon_ver = '2.4.71'
_drm_nouveau_ver = '2.4.66'
_drm_etnaviv_ver = '2.4.89'
......
......@@ -486,6 +486,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
else if (initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(size, ws->info.gart_page_size);
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, &bo->u.real.kms_handle);
amdgpu_add_buffer_to_global_list(bo);
return bo;
......@@ -1353,6 +1355,8 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, &bo->u.real.kms_handle);
amdgpu_add_buffer_to_global_list(bo);
util_hash_table_set(ws->bo_export_table, bo->bo, bo);
......@@ -1459,6 +1463,8 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
amdgpu_add_buffer_to_global_list(bo);
amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, &bo->u.real.kms_handle);
return (struct pb_buffer*)bo;
error_va_map:
......
......@@ -66,6 +66,8 @@ struct amdgpu_winsys_bo {
bool use_reusable_pool;
struct list_head global_list_item;
uint32_t kms_handle;
} real;
struct {
struct pb_slab_entry entry;
......
......@@ -37,6 +37,10 @@
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
#endif
#ifndef AMDGPU_CHUNK_ID_BO_HANDLES
#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
#endif
DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", false)
/* FENCES */
......@@ -1290,11 +1294,14 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
amdgpu_bo_list_handle bo_list = NULL;
uint64_t seq_no = 0;
bool has_user_fence = amdgpu_cs_has_user_fence(cs);
bool use_bo_list_create = ws->info.drm_minor < 27;
struct drm_amdgpu_bo_list_in bo_list_in;
/* Create the buffer list.
* Use a buffer list containing all allocated buffers if requested.
*/
/* Prepare the buffer list. */
if (ws->debug_all_bos) {
/* The buffer list contains all buffers. This is a slow path that
* ensures that no buffer is missing in the BO list.
*/
struct amdgpu_winsys_bo *bo;
amdgpu_bo_handle *handles;
unsigned num = 0;
......@@ -1314,7 +1321,38 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
goto cleanup;
}
} else if (!use_bo_list_create) {
/* Standard path passing the buffer list via the CS ioctl. */
if (!amdgpu_add_sparse_backing_buffers(cs)) {
fprintf(stderr, "amdgpu: amdgpu_add_sparse_backing_buffers failed\n");
r = -ENOMEM;
goto cleanup;
}
struct drm_amdgpu_bo_list_entry *list =
alloca(cs->num_real_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
unsigned num_handles = 0;
for (i = 0; i < cs->num_real_buffers; ++i) {
struct amdgpu_cs_buffer *buffer = &cs->real_buffers[i];
if (buffer->bo->is_local)
continue;
assert(buffer->u.real.priority_usage != 0);
list[num_handles].bo_handle = buffer->bo->u.real.kms_handle;
list[num_handles].bo_priority = (util_last_bit(buffer->u.real.priority_usage) - 1) / 2;
++num_handles;
}
bo_list_in.operation = ~0;
bo_list_in.list_handle = ~0;
bo_list_in.bo_number = num_handles;
bo_list_in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
bo_list_in.bo_info_ptr = (uint64_t)(uintptr_t)list;
} else {
/* Legacy path creating the buffer list handle and passing it to the CS ioctl. */
unsigned num_handles;
if (!amdgpu_add_sparse_backing_buffers(cs)) {
......@@ -1356,7 +1394,7 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
if (acs->ctx->num_rejected_cs) {
r = -ECANCELED;
} else {
struct drm_amdgpu_cs_chunk chunks[5];
struct drm_amdgpu_cs_chunk chunks[6];
unsigned num_chunks = 0;
/* Convert from dwords to bytes. */
......@@ -1447,6 +1485,14 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
num_chunks++;
}
/* BO list */
if (!use_bo_list_create) {
chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_bo_list_in) / 4;
chunks[num_chunks].chunk_data = (uintptr_t)&bo_list_in;
num_chunks++;
}
assert(num_chunks <= ARRAY_SIZE(chunks));
r = amdgpu_cs_submit_raw(ws->dev, acs->ctx->ctx, bo_list,
......
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