Commit bd25e23b authored by Jerome Glisse's avatar Jerome Glisse

r600g: simplify states

Directly build PM4 packet, avoid using malloc (no states are
bigger than 128 dwords), remove unecessary informations,
remove pm4 building in favor of prebuild pm4 packet.
Signed-off-by: 's avatarJerome Glisse <jglisse@redhat.com>
parent b5c07b92
......@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
unsigned srcx, unsigned srcy, unsigned srcz,
unsigned width, unsigned height)
{
util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
src, subsrc, srcx, srcy, srcz, width, height);
}
......@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
memcpy(bo->data, vbo, 128);
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return -ENOMEM;
......@@ -199,33 +199,35 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return -ENOMEM;
}
bstates->vs_resource0 = rstate;
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
if (rstate == NULL) {
return -ENOMEM;
}
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......@@ -303,7 +305,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
......@@ -321,6 +323,8 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
rstate->nbo = 2;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -374,7 +378,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
}
radeon_bo_unmap(rscreen->rw, bo);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
if (rstate == NULL) {
radeon_bo_decref(rscreen->rw, bo);
return NULL;
......@@ -391,6 +395,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
rstate->bo[0] = bo;
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
......@@ -403,7 +408,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
rstate = radeon_state(rscreen->rw, R600_VGT);
if (rstate == NULL)
return NULL;
......@@ -425,7 +430,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
rstate = radeon_state(rscreen->rw, R600_DRAW);
if (rstate == NULL)
return NULL;
......@@ -448,7 +453,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
if (rstate == NULL)
return NULL;
......@@ -471,7 +476,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
if (rstate == NULL)
return NULL;
......@@ -500,7 +505,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
rstate = radeon_state(rscreen->rw, R600_DSA);
if (rstate == NULL)
return NULL;
......@@ -524,7 +529,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
rstate = radeon_state(rscreen->rw, R600_BLEND);
if (rstate == NULL)
return NULL;
......@@ -543,7 +548,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
if (rstate == NULL)
return NULL;
......@@ -786,10 +791,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
r600_queries_suspend(ctx);
/* schedule draw*/
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
r = radeon_ctx_set_draw(rctx->ctx, draw);
if (r == -EBUSY) {
r600_flush(ctx, 0, NULL);
r = radeon_ctx_set_draw_new(rctx->ctx, draw);
r = radeon_ctx_set_draw(rctx->ctx, draw);
}
if (r) {
goto out;
......
......@@ -53,12 +53,10 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
/* suspend queries */
r600_queries_suspend(ctx);
if (radeon_ctx_pm4(rctx->ctx))
goto out;
/* FIXME dumping should be removed once shader support instructions
* without throwing bad code
*/
if (!rctx->ctx->cpm4)
if (!rctx->ctx->id)
goto out;
sprintf(dname, "gallium-%08d.bof", dc);
if (dc < 2) {
......@@ -73,8 +71,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
}
dc++;
out:
rctx->ctx = radeon_ctx_decref(rctx->ctx);
rctx->ctx = radeon_ctx(rscreen->rw);
radeon_ctx_clear(rctx->ctx);
/* resume queries */
r600_queries_resume(ctx);
}
......@@ -218,7 +215,7 @@ static void r600_init_config(struct r600_context *rctx)
num_es_stack_entries = 0;
break;
}
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
switch (family) {
......
......@@ -101,19 +101,21 @@ static int r600_draw_common(struct r600_draw *draw)
rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
if (vs_resource == NULL)
return -ENOMEM;
vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
vs_resource->nbo = 1;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
S_038008_DATA_FORMAT(format);
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
r = radeon_draw_set_new(rctx->draw, vs_resource);
......@@ -121,22 +123,29 @@ static int r600_draw_common(struct r600_draw *draw)
return r;
}
/* FIXME start need to change winsys */
draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
if (draw->index_buffer) {
draw->draw = radeon_state(rscreen->rw, R600_DRAW);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
rbuffer = (struct r600_resource*)draw->index_buffer;
draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
draw->draw->nbo = 1;
draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
} else {
draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
if (draw->draw == NULL)
return -ENOMEM;
draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
}
r = radeon_draw_set_new(rctx->draw, draw->draw);
if (r)
return r;
draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
draw->vgt = radeon_state(rscreen->rw, R600_VGT);
if (draw->vgt == NULL)
return -ENOMEM;
draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
......@@ -145,23 +154,18 @@ static int r600_draw_common(struct r600_draw *draw)
draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
r = radeon_draw_set_new(rctx->draw, draw->vgt);
if (r)
return r;
/* FIXME */
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
if (r == -EBUSY) {
r600_flush(draw->ctx, 0, NULL);
r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
}
if (r)
return r;
rctx->draw = radeon_draw_duplicate(rctx->draw);
return 0;
}
......
......@@ -36,10 +36,11 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......@@ -55,10 +56,11 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
struct r600_screen *rscreen = rctx->screen;
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
rstate = radeon_state(rscreen->rw, R600_QUERY_END);
if (rstate == NULL)
return NULL;
rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
......
......@@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
unsigned i, tmp;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
state = radeon_state(rscreen->rw, R600_VS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < 10; i++) {
......@@ -151,6 +151,8 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->nbo = 2;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
return radeon_state_pm4(state);
}
......@@ -165,7 +167,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rasterizer = &rctx->rasterizer->state.rasterizer;
rpshader->rstate = radeon_state_decref(rpshader->rstate);
state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
state = radeon_state(rscreen->rw, R600_PS_SHADER);
if (state == NULL)
return -ENOMEM;
for (i = 0; i < rshader->ninput; i++) {
......@@ -204,6 +206,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
rpshader->rstate->nbo = 1;
rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
return radeon_state_pm4(state);
}
......
This diff is collapsed.
......@@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
rstate = radeon_state(rscreen->rw, R600_SCISSOR);
if (rstate == NULL)
return NULL;
......@@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
unsigned format, swap, ntype;
const struct util_format_description *desc;
rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
rstate = radeon_state(rscreen->rw, R600_CB0);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
......@@ -742,13 +742,16 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
rstate->nbo = 3;
color_info = S_0280A0_SOURCE_FORMAT(1);
}
rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
S_028060_SLICE_TILE_MAX(slice);
if (radeon_state_pm4(rstate)) {
......@@ -766,7 +769,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
struct r600_resource *rbuffer;
unsigned pitch, slice, format;
rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
rstate = radeon_state(rscreen->rw, R600_DB);
if (rstate == NULL)
return NULL;
rbuffer = &rtexture->resource;
......@@ -784,6 +787,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
......@@ -815,7 +819,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
......
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......@@ -153,47 +153,3 @@ struct radeon *radeon_decref(struct radeon *radeon)
free(radeon);
return NULL;
}
int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
{
unsigned i, j;
for (i = 0; i < radeon->ntype; i++) {
if (radeon->type[i].range_start) {
if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
*typeid = i;
j = offset - radeon->type[i].range_start;
j /= radeon->type[i].stride;
*stateid = radeon->type[i].id + j;
*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
return 0;
}
} else {
for (j = 0; j < radeon->type[i].nstates; j++) {
if (radeon->type[i].regs[j].offset == offset) {
*typeid = i;
*stateid = radeon->type[i].id;
*id = j;
return 0;
}
}
}
}
fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
return -EINVAL;
}
unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
{
unsigned i;
for (i = 0; i < radeon->ntype - 1; i++) {
if (radeon->type[i].id == id)
return i;
if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
return i;
}
if (radeon->type[i].id == id)
return i;
return -1;
}
This diff is collapsed.
......@@ -76,8 +76,6 @@ int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
{
if (state == NULL)
return 0;
if (state->type >= draw->radeon->ntype)
return -EINVAL;
draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
draw->state[state->id] = state;
return 0;
......@@ -102,6 +100,7 @@ int radeon_draw_check(struct radeon_draw *draw)
for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
if (draw->state[i]) {
draw->cpm4 += draw->state[i]->cpm4;
draw->cpm4 += draw->radeon->type[draw->state[i]->id].header_cpm4;
}
}
return 0;
......
......@@ -30,34 +30,26 @@ struct radeon_ctx;
* radeon functions
*/
typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
struct radeon_register {
unsigned offset;
unsigned need_reloc;
unsigned bo_id;
char name[64];
};
struct radeon_type {
unsigned npm4;
unsigned id;
unsigned range_start;
unsigned range_end;
unsigned stride;
unsigned immediate;
char name[64];
unsigned nstates;
radeon_state_pm4_t pm4;
const struct radeon_register *regs;
const u32 *header_pm4;
const u32 header_cpm4;
const u32 *state_pm4;
const u32 state_cpm4;
const u32 flush_flags;
const u32 dirty_flags;
};
typedef int (*radeon_ctx_bo_flush_t)(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement);
struct radeon {
int fd;
int refcount;
unsigned device;
unsigned family;
unsigned nstate;
unsigned ntype;
const struct radeon_type *type;
radeon_ctx_bo_flush_t bo_flush;
};
extern struct radeon *radeon_new(int fd, unsigned device);
......@@ -68,12 +60,9 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
int radeon_ctx_draw(struct radeon_ctx *ctx);
int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
unsigned id, unsigned *placement);
/*
* r600/r700 context functions
......@@ -90,7 +79,6 @@ extern int radeon_state_register_set(struct radeon_state *state, unsigned offset
extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
extern int radeon_state_pm4_generic(struct radeon_state *state);
extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
/*
* radeon draw functions
......
......@@ -32,52 +32,29 @@
/*
* state core functions
*/
struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
struct radeon_state *radeon_state(struct radeon *radeon, u32 id)
{
struct radeon_state *state;
if (type > radeon->ntype) {
fprintf(stderr, "%s invalid type %d\n", __func__, type);
return NULL;
}
if (id > radeon->nstate) {
fprintf(stderr, "%s invalid state id %d\n", __func__, id);
return NULL;
}
state = calloc(1, sizeof(*state));
if (state == NULL)
return NULL;
state->radeon = radeon;
state->type = type;
state->id = id;
state->refcount = 1;
state->npm4 = radeon->type[type].npm4;
state->nstates = radeon->type[type].nstates;
state->states = calloc(1, state->nstates * 4);
state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
if (state->states == NULL || state->pm4 == NULL) {
radeon_state_decref(state);
return NULL;
}
state->cpm4 = radeon->type[id].state_cpm4;
memcpy(state->states, radeon->type[id].state_pm4, radeon->type[id].state_cpm4 * 4);
return state;
}
struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
{
struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
struct radeon_state *nstate = radeon_state(state->radeon, state->id);
unsigned i;
if (state == NULL)
return NULL;
nstate->cpm4 = state->cpm4;
nstate->nbo = state->nbo;
nstate->nreloc = state->nreloc;
memcpy(nstate->states, state->states, state->nstates * 4);
memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
memcpy(nstate->placement, state->placement, 8 * 4);
memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
*nstate = *state;
for (i = 0; i < state->nbo; i++) {
nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
}
......@@ -102,9 +79,6 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
for (i = 0; i < state->nbo; i++) {
state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
}
free(state->immd);
free(state->states);
free(state->pm4);
memset(state, 0, sizeof(*state));
free(state);
return NULL;
......@@ -145,24 +119,8 @@ static u32 crc32(void *d, size_t len)
int radeon_state_pm4(struct radeon_state *state)
{
int r;
if (state == NULL || state->cpm4)
if (state == NULL)
return 0;
r = state->radeon->type[state->type].pm4(state);
if (r) {
fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
__func__, state->type, state->id);
return r;
}
state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
return 0;
}
int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
{
state->reloc_pm4_id[state->nreloc] = id;
state->reloc_bo_id[state->nreloc] = bo_id;
state->nreloc++;
state->pm4_crc = crc32(state->states, state->cpm4 * 4);
return 0;
}
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