1. 26 Oct, 2018 1 commit
    • Rob Clark's avatar
      freedreno: import libdrm_freedreno + redesign submit · f3cc0d27
      Rob Clark authored
      In the pursuit of lowering driver overhead, it became clear that some
      amount of redesign of how libdrm_freedreno constructs the submit ioctl
      would be needed.  In particular, as the gallium driver is starting to
      make heavier use of CP_SET_DRAW_STATE state groups/objects, the over-
      head of tracking cmd buffers and relocs becomes too much.  And for
      "streaming" state, which isn't ever reused (like uniform uploads) the
      overhead of allocating/freeing ringbuffer[1] objects is too high.
      
      This redesign makes two main changes:
      
       1) Introduces a fd_submit object for tracking bos and cmds table
          for the submit ioctl, making ringbuffer objects more light-
          weight.  This was previously done in the ringbuffer.  But we
          have many ringbuffer instances involved in a submit (gmem +
          draw + potentially 1000's of state-group rbs), and only need
          a single bos and cmds table.  (Reloc table is still per-rb)
      
          The submit is also a convenient place for a slab allocator for
          ringbuffer objects.  Other options would have required locking
          because, while we can guarantee allocations will only happen on
          a single thread, free's could happen either on the application
          thread or the flush_queue thread.  With the slab allocator in
          the submit object, any frees that happen on the flush_queue
          thread happen after we know that the application thread is done
          with the submit.
      
       2) Introduce a new "softpin" msm_ringbuffer_sp implementation that
          does not use relocs and only has cmds table entries for IB1 (ie.
          the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER
          to from the RB).  To do this properly will require some updates
          on the kernel side, so whether you get the softpin or legacy
          submit/ringbuffer implementation at runtime depends on your
          kernel version.
      
      To make all these changes in libdrm would basically require adding a
      libdrm_freedreno2, so this is a good point to just pull the libdrm code
      into mesa.  Plus it allows for using mesa's hashtable, slab allocator,
      etc.  And it lets us have asserts enabled for debug mesa buids but
      omitted for release builds.  And it makes life easier if further API
      changes become necessary.
      
      At this point I haven't tried to pull in the kgsl backend.  Although
      I left the level of vfunc indirection which would make it possible
      to have other backends.  (And this was convenient to keep to allow
      for the "softpin" ringbuffer to coexist.)
      
      NOTE: if bisecting a build error takes you here, try a clean build.
      There are a bunch of ways things can go wrong if you still have
      libdrm_freedreno cflags.
      
      [1] "ringbuffer" is probably a bad name, the only level of cmdstream
          buffer that is actually a ring is RB managed by kernel.  User-
          space cmdstream is all IB1/IB2 and state-groups.
      Reviewed-by: 's avatarKristian H. Kristensen <hoegsberg@chromium.org>
      Reviewed-by: 's avatarEric Engestrom <eric.engestrom@intel.com>
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      f3cc0d27
  2. 17 Oct, 2018 1 commit
    • Rob Clark's avatar
      freedreno/ir3: move binning_pass out of shader variant key · 2e9c08c0
      Rob Clark authored
      Prep work for a following patch, that introduces a cache to map from
      program state (all shader stages) plus variant key to pre-baked hw
      state (which could be emit'd via CP_SET_DRAW_STATE, for example).
      To do that, we really want the variant key to be immutable, and to
      treat the binning pass shader as an extra shader stage, rather than
      as a VS variant.
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      2e9c08c0
  3. 27 Sep, 2018 1 commit
    • Rob Clark's avatar
      freedreno: simplify pctx->clear() · 5bb96bf7
      Rob Clark authored
      This is defined to always clear the entire surface(s) specified,
      regardless of scissor state.. mesa/st will turn scissored clears
      into a draw.  So rip about a bunch of unnecessary machinery.
      
      Also remove a comment that was obsolete since using u_blitter to
      turn clear into draw (for the cases where there isn't a hw blitter
      fast-path).
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      5bb96bf7
  4. 30 Jul, 2018 1 commit
  5. 18 Jul, 2018 1 commit
  6. 21 Jun, 2018 1 commit
  7. 14 Nov, 2017 1 commit
  8. 24 Oct, 2017 1 commit
  9. 07 Jun, 2017 1 commit
  10. 16 May, 2017 1 commit
  11. 13 May, 2017 1 commit
  12. 10 May, 2017 1 commit
    • Marek Olšák's avatar
      gallium: remove pipe_index_buffer and set_index_buffer · 330d0607
      Marek Olšák authored
      pipe_draw_info::indexed is replaced with index_size. index_size == 0 means
      non-indexed.
      
      Instead of pipe_index_buffer::offset, pipe_draw_info::start is used.
      For indexed indirect draws, pipe_draw_info::start is added to the indirect
      start. This is the only case when "start" affects indirect draws.
      
      pipe_draw_info::index is a union. Use either index::resource or
      index::user depending on the value of pipe_draw_info::has_user_indices.
      
      v2: fixes for nine, svga
      330d0607
  13. 18 Apr, 2017 3 commits
  14. 22 Jan, 2017 2 commits
  15. 27 Dec, 2016 1 commit
    • Rob Clark's avatar
      freedreno/a5xx: transform-feedback support · d10c5a24
      Rob Clark authored
      We'll need to revisit when adding hw binning pass support, whether we
      can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
      needed to move it to the binning stage.
      
      Still some failing piglits but most tests pass and the common cases seem
      to work.
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      d10c5a24
  16. 30 Nov, 2016 1 commit
  17. 07 Oct, 2016 1 commit
  18. 16 Aug, 2016 1 commit
  19. 13 Aug, 2016 1 commit
  20. 30 Jul, 2016 3 commits
    • Rob Clark's avatar
      freedreno: move needs_wfi into batch · e6bfe1c7
      Rob Clark authored
      This is also used in gmem code, which executes from the "bottom half"
      (ie. from the flush_queue worker thread), so it cannot be in fd_context.
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      e6bfe1c7
    • Rob Clark's avatar
      freedreno: move more batch related tracking to fd_batch · f02a64db
      Rob Clark authored
      To flush batches out of order, the gmem code needs to not depend on
      state from fd_context (since that may apply to a more recent batch).
      So this all moves into batch.
      
      The one exception is the gmem/pipe/tile state itself.  But this is
      only used from gmem code (and batches are flushed serially).  The
      alternative would be having to re-calculate GMEM layout on every
      batch, even if the dimensions of the render targets are the same.
      
      Note: This opens up the possibility of pushing gmem/submit into a
      helper thread.
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      f02a64db
    • Rob Clark's avatar
      freedreno: introduce fd_batch · 9bbd239a
      Rob Clark authored
      Introduce the batch object, to track a batch/submit's worth of
      ringbuffers and other bookkeeping.  In this first step, just move
      the ringbuffers into batch, since that is mostly uninteresting
      churn.
      
      For now there is just a single batch at a time.  Note that one
      outcome of this change is that rb's are allocated/freed on each
      use.  But the expectation is that the bo pool in libdrm_freedreno
      will save us the GEM bo alloc/free which was the initial reason
      to implement a rb pool in gallium.
      
      The purpose of the batch is to eventually facilitate out-of-order
      rendering, with batches associated to framebuffer state, and
      tracking the dependencies on other batches.
      Signed-off-by: 's avatarRob Clark <robdclark@gmail.com>
      9bbd239a
  21. 04 May, 2016 2 commits
  22. 30 Apr, 2016 2 commits
  23. 24 Apr, 2016 2 commits
  24. 19 Apr, 2016 1 commit
    • Rob Clark's avatar
      freedreno/a4xx: lower srgb in shader for astc textures · 899bd63a
      Rob Clark authored
      This *seems* like a hw bug, and maybe only applies to certain a4xx
      variants/revisions.  But setting the SRGB bit in sampler view state
      (texconst0) causes invalid alpha for ASTC textures.  Work around this
      by doing the srgb->linear conversion in the shader instead.
      
      This fixes 392 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
      
      (The remaining fails seem to be a bug w/ ASTC + linear filtering, also
      possibly a420.0 specific.)
      Signed-off-by: 's avatarRob Clark <robclark@freedesktop.org>
      899bd63a
  25. 13 Apr, 2016 1 commit
    • Rob Clark's avatar
      freedreno/a4xx: rasterizer_discard support · 46e9bbc9
      Rob Clark authored
      This one is slightly annoying, since trying to write RBRC from draw
      would clobber values set in the tiling/gmem code.  We could do command-
      stream patching for RBRC, as is done on a3xx.  Although since it seems
      to be a rarely used feature, it is easier just to do RMW to set/clear
      the bit.
      
      Fixes dEQP-GLES3.functional.rasterizer_discard.basic.write_depth_triangles
      and related tests.
      
      a3xx still needs the same feature, although there it probably makes more
      sense to take advantage of the existing cmdstream patching which is
      required for RBRC for other reasons.
      Signed-off-by: 's avatarRob Clark <robclark@freedesktop.org>
      46e9bbc9
  26. 13 Mar, 2016 2 commits
  27. 21 Nov, 2015 1 commit
  28. 18 Nov, 2015 1 commit
  29. 24 Oct, 2015 1 commit
  30. 17 Sep, 2015 1 commit
  31. 12 Aug, 2015 1 commit