Commit 64485cb2 authored by Sudi Das's avatar Sudi Das Committed by Tamar Christina
Browse files

AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV
instructions. These instructions needed special infrastructure to support
[base]! style for addressing mode. That is also removed now.

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (parse_address_main): Remove support for
	[base]! address expression.
	(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
	(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
	and stgv.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** include/ChangeLog ***

	* opcode/aarch64.h (enum aarch64_opnd): Remove
	AARCH64_OPND_ADDR_SIMPLE_2.
	(enum aarch64_insn_class): Remove ldstgv_indexed.

*** opcodes/ChangeLog ***

	* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
	* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
	* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
	* aarch64-dis.h (ext_addr_simple_2): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Remove
	case for ldstgv_indexed.
	(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
	* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
	(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

(cherry picked from commit 550fd7bf)
parent 8bc06c98
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
......
......@@ -3381,7 +3381,6 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
[base,Wm,(S|U)XTW {#imm}]
Pre-indexed
[base,#imm]!
[base]! // in ld/stgv
Post-indexed
[base],#imm
[base],Xm // in SIMD ld/st structure
......@@ -3690,11 +3689,10 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
}
/* If at this point neither .preind nor .postind is set, we have a
bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
as a shorthand for [Rn,#0]. */
bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */
if (operand->addr.preind == 0 && operand->addr.postind == 0)
{
if (operand->type != AARCH64_OPND_ADDR_SIMPLE_2 && operand->addr.writeback)
if (operand->addr.writeback)
{
/* Reject [Rn]! */
set_syntax_error (_("missing offset in the pre-indexed address"));
......@@ -6148,7 +6146,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_ADDR_SIMPLE:
case AARCH64_OPND_ADDR_SIMPLE_2:
case AARCH64_OPND_SIMD_ADDR_SIMPLE:
{
/* [<Xn|SP>{, #<simm>}] */
......@@ -6158,8 +6155,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
po_misc_or_fail (parse_address (&str, info));
if (info->addr.pcrel || info->addr.offset.is_reg
|| !info->addr.preind || info->addr.postind
|| (info->addr.writeback
&& operands[i] != AARCH64_OPND_ADDR_SIMPLE_2))
|| info->addr.writeback)
{
set_syntax_error (_("invalid addressing mode"));
goto failure;
......@@ -6182,8 +6178,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
}
po_char_or_fail (']');
if (operands[i] == AARCH64_OPND_ADDR_SIMPLE_2)
po_char_or_fail ('!');
break;
}
......@@ -6782,13 +6776,6 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
break;
case ldstgv_indexed:
/* Load operations must load different registers. */
if ((opcode->opcode & (1 << 22))
&& opnds[0].reg.regno == opnds[1].addr.base_regno)
as_warn (_("unpredictable load of register -- `%s'"), str);
break;
case ldstpair_off:
case ldstnapair_offs:
case ldstpair_indexed:
......
......@@ -121,14 +121,3 @@ Disassembly of section \.text:
.*: d960001f ldg xzr, \[x0\]
.*: d96ff000 ldg x0, \[x0, #4080\]
.*: d9700000 ldg x0, \[x0, #-4096\]
.*: d9e0001b ldgv x27, \[x0\]!
.*: d9e00360 ldgv x0, \[x27\]!
.*: d9e00379 ldgv x25, \[x27\]!
.*: d9e003e0 ldgv x0, \[sp\]!
.*: d9e0001f ldgv xzr, \[x0\]!
.*: d9a00000 stgv x0, \[x0\]!
.*: d9a0001b stgv x27, \[x0\]!
.*: d9a00360 stgv x0, \[x27\]!
.*: d9a00379 stgv x25, \[x27\]!
.*: d9a003e0 stgv x0, \[sp\]!
.*: d9a0001f stgv xzr, \[x0\]!
......@@ -30,14 +30,6 @@ func:
\op [sp], #-4096
.endm
.macro expand_ldg_bulk op
\op x27, [x0]!
\op x0, [x27]!
\op x25, [x27]!
\op x0, [sp]!
\op xzr, [x0]!
.endm
# IRG
expand_3_reg irg
irg sp, x0
......@@ -106,8 +98,3 @@ func:
ldg xzr, [x0, #0]
ldg x0, [x0, #4080]
ldg x0, [x0, #-4096]
expand_ldg_bulk ldgv
stgv x0, [x0]!
expand_ldg_bulk stgv
......@@ -12,9 +12,6 @@
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
[^:]*:[0-9]+: Warning: unpredictable load of register -- `ldgv x1,\[x1\]!'
[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `ldgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 2 must be a writeback address with base register \(no offset\) -- `stgv x1,\[x2\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
......@@ -40,7 +37,3 @@
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgv sp,\[x1\]!'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldgv x0,\[xzr\]!'
[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgv sp,\[x1\]!'
[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stgv x0,\[xzr\]!'
......@@ -20,14 +20,6 @@ func:
stgp x1, x2, [x3, #33]
stgp x1, x2, [x3, #-1025]
# LDGV : Warn for Xt == Xn
# STGV : Sould not warn for above
ldgv x1, [x1]!
stgv x1, [x1]!
# Error for no writeback
ldgv x1, [x2]
stgv x1, [x2]
# Illegal SP/XZR registers
irg xzr, x2, x3
irg x1, xzr, x3
......@@ -54,7 +46,3 @@ func:
stgp x0, x0, [xzr]
ldg sp, [x0, #16]
ldg x0, [xzr, #16]
ldgv sp, [x1]!
ldgv x0, [xzr]!
stgv sp, [x1]!
stgv x0, [xzr]!
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Remove
AARCH64_OPND_ADDR_SIMPLE_2.
(enum aarch64_insn_class): Remove ldstgv_indexed.
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
......
......@@ -275,7 +275,6 @@ enum aarch64_opnd
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
......@@ -562,7 +561,6 @@ enum aarch64_insn_class
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
ldstgv_indexed,
loadlit,
log_imm,
log_shift,
......
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
2019-01-23 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation.
......
This diff is collapsed.
......@@ -618,17 +618,6 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
/* Encode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
bfd_boolean
aarch64_ins_addr_simple_2 (const aarch64_operand *self,
const aarch64_opnd_info *info, aarch64_insn *code,
const aarch64_inst *inst,
aarch64_operand_error *errors)
{
return aarch64_ins_addr_simple (self, info, code, inst, errors);
}
/* Encode the address operand for e.g.
STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
bfd_boolean
......
......@@ -59,7 +59,6 @@ AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple_2);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
......
This diff is collapsed.
......@@ -985,23 +985,6 @@ aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
/* Decode the address operand for e.g. STGV <Xt>, [<Xn|SP>]!. */
bfd_boolean
aarch64_ext_addr_simple_2 (const aarch64_operand *self ATTRIBUTE_UNUSED,
aarch64_opnd_info *info,
aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
/* Rn */
info->addr.base_regno = extract_field (FLD_Rn, code, 0);
info->addr.writeback = 1;
info->addr.preind = 1;
return TRUE;
}
/* Decode the address operand for e.g.
stlur <Xt>, [<Xn|SP>{, <amount>}]. */
bfd_boolean
......
......@@ -82,7 +82,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple_2);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
......
......@@ -107,7 +107,6 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a writeback address with base register (no offset)"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
......@@ -257,24 +256,24 @@ static const unsigned op_enum_table [] =
925,
931,
932,
983,
984,
985,
986,
987,
988,
12,
636,
637,
1178,
1180,
1182,
1184,
992,
1183,
990,
1181,
1179,
318,
624,
635,
634,
990,
988,
631,
628,
620,
......@@ -284,7 +283,7 @@ static const unsigned op_enum_table [] =
630,
632,
633,
1000,
998,
664,
667,
670,
......@@ -301,17 +300,17 @@ static const unsigned op_enum_table [] =
391,
413,
415,
1253,
1258,
1251,
1250,
1254,
1256,
1249,
1248,
1252,
1259,
1261,
1263,
1262,
1258,
1264,
1260,
1266,
1265,
1263,
131,
};
......
......@@ -1602,7 +1602,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case ldst_imm9:
case ldstpair_indexed:
case ldstgv_indexed:
case asisdlsep:
case asisdlsop:
if (opnd->addr.writeback == 0)
......@@ -3557,11 +3556,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "[%s]", name);
break;
case AARCH64_OPND_ADDR_SIMPLE_2:
name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
snprintf (buf, size, "[%s]!", name);
break;
case AARCH64_OPND_ADDR_REGOFF:
case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR:
......
......@@ -3324,8 +3324,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
MEMTAG_INSN ("ldgv", 0xd9e00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
MEMTAG_INSN ("stgv", 0xd9a00000, 0xfffffc00, ldstgv_indexed, OP2 (Rt, ADDR_SIMPLE_2), QL_STLX, 0),
/* Limited Ordering Regions load/store instructions. */
_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
......@@ -4650,8 +4648,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_imm26), "26-bit PC-relative address") \
Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
"an address with base register (no offset)") \
Y(ADDRESS, addr_simple_2, "ADDR_SIMPLE_2", 0, F(), \
"a writeback address with base register (no offset)") \
Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
"an address with register offset") \
Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
......
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