Commit e23eba97 authored by Nick Clifton's avatar Nick Clifton
Browse files

Add support for RISC-V architecture.

bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
parent 4e56efac
2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
Andrew Waterman <andrew@sifive.com>
Add support for RISC-V architecture.
* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.
2016-10-31 Alan Modra <amodra@gmail.com>
PR 20748
......
......@@ -148,6 +148,7 @@ ALL_MACHINES = \
cpu-plugin.lo \
cpu-powerpc.lo \
cpu-rs6000.lo \
cpu-riscv.lo \
cpu-rl78.lo \
cpu-rx.lo \
cpu-s390.lo \
......@@ -235,6 +236,7 @@ ALL_MACHINES_CFILES = \
cpu-plugin.c \
cpu-powerpc.c \
cpu-rs6000.c \
cpu-riscv.c \
cpu-rl78.c \
cpu-rx.c \
cpu-s390.c \
......@@ -671,18 +673,21 @@ BFD64_BACKENDS = \
elf64-hppa.lo \
elf64-ia64.lo \
elf64-ia64-vms.lo \
elfxx-ia64.lo \
elfn32-mips.lo \
elf64-mips.lo \
elfxx-mips.lo \
elf64-mmix.lo \
elf64-ppc.lo \
elf32-riscv.lo \
elf64-riscv.lo \
elfxx-riscv.lo \
elf64-s390.lo \
elf64-sh64.lo \
elf64-sparc.lo \
elf64-tilegx.lo \
elf64-x86-64.lo \
elf64.lo \
elfn32-mips.lo \
elfxx-ia64.lo \
elfxx-mips.lo \
mach-o-aarch64.lo \
mach-o-x86-64.lo \
mmo.lo \
......@@ -722,6 +727,7 @@ BFD64_BACKENDS_CFILES = \
elfxx-aarch64.c \
elfxx-ia64.c \
elfxx-mips.c \
elfxx-riscv.c \
mach-o-aarch64.c \
mach-o-x86-64.c \
mmo.c \
......@@ -785,7 +791,9 @@ SOURCE_CFILES = \
BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c
elf32-ia64.c elf64-ia64.c \
elf32-riscv.c elf64-riscv.c \
peigen.c pepigen.c pex64igen.c
CFILES = $(SOURCE_CFILES) $(BUILD_CFILES)
......@@ -955,6 +963,18 @@ elf64-ia64.c : elfnn-ia64.c
$(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
mv -f elf64-ia64.new elf64-ia64.c
elf32-riscv.c : elfnn-riscv.c
rm -f elf32-riscv.c
echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
mv -f elf32-riscv.new elf32-riscv.c
elf64-riscv.c : elfnn-riscv.c
rm -f elf64-riscv.c
echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
mv -f elf64-riscv.new elf64-riscv.c
peigen.c : peXXigen.c
rm -f peigen.c
$(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
......
......@@ -481,6 +481,7 @@ ALL_MACHINES = \
cpu-plugin.lo \
cpu-powerpc.lo \
cpu-rs6000.lo \
cpu-riscv.lo \
cpu-rl78.lo \
cpu-rx.lo \
cpu-s390.lo \
......@@ -568,6 +569,7 @@ ALL_MACHINES_CFILES = \
cpu-plugin.c \
cpu-powerpc.c \
cpu-rs6000.c \
cpu-riscv.c \
cpu-rl78.c \
cpu-rx.c \
cpu-s390.c \
......@@ -1006,18 +1008,21 @@ BFD64_BACKENDS = \
elf64-hppa.lo \
elf64-ia64.lo \
elf64-ia64-vms.lo \
elfxx-ia64.lo \
elfn32-mips.lo \
elf64-mips.lo \
elfxx-mips.lo \
elf64-mmix.lo \
elf64-ppc.lo \
elf32-riscv.lo \
elf64-riscv.lo \
elfxx-riscv.lo \
elf64-s390.lo \
elf64-sh64.lo \
elf64-sparc.lo \
elf64-tilegx.lo \
elf64-x86-64.lo \
elf64.lo \
elfn32-mips.lo \
elfxx-ia64.lo \
elfxx-mips.lo \
mach-o-aarch64.lo \
mach-o-x86-64.lo \
mmo.lo \
......@@ -1057,6 +1062,7 @@ BFD64_BACKENDS_CFILES = \
elfxx-aarch64.c \
elfxx-ia64.c \
elfxx-mips.c \
elfxx-riscv.c \
mach-o-aarch64.c \
mach-o-x86-64.c \
mmo.c \
......@@ -1122,7 +1128,9 @@ SOURCE_CFILES = \
BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c
elf32-ia64.c elf64-ia64.c \
elf32-riscv.c elf64-riscv.c \
peigen.c pepigen.c pex64igen.c
CFILES = $(SOURCE_CFILES) $(BUILD_CFILES)
SOURCE_HFILES = \
......@@ -1412,6 +1420,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-riscv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rl78.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@
......@@ -1501,6 +1510,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-riscv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@
......@@ -1532,6 +1542,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sh64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
......@@ -1543,6 +1554,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-ia64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-riscv.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-sparc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-tilegx.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epoc-pe-arm.Plo@am__quote@
......@@ -2080,6 +2092,18 @@ elf64-ia64.c : elfnn-ia64.c
$(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
mv -f elf64-ia64.new elf64-ia64.c
elf32-riscv.c : elfnn-riscv.c
rm -f elf32-riscv.c
echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
mv -f elf32-riscv.new elf32-riscv.c
elf64-riscv.c : elfnn-riscv.c
rm -f elf64-riscv.c
echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
mv -f elf64-riscv.new elf64-riscv.c
peigen.c : peXXigen.c
rm -f peigen.c
$(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new
......
......@@ -457,6 +457,9 @@ DESCRIPTION
.#define bfd_mach_cris_v0_v10 255
.#define bfd_mach_cris_v32 32
.#define bfd_mach_cris_v10_v32 1032
. bfd_arch_riscv,
.#define bfd_mach_riscv32 132
.#define bfd_mach_riscv64 164
. bfd_arch_rl78,
.#define bfd_mach_rl78 0x75
. bfd_arch_rx, {* Renesas RX. *}
......@@ -628,6 +631,7 @@ extern const bfd_arch_info_type bfd_pj_arch;
extern const bfd_arch_info_type bfd_plugin_arch;
extern const bfd_arch_info_type bfd_powerpc_archs[];
#define bfd_powerpc_arch bfd_powerpc_archs[0]
extern const bfd_arch_info_type bfd_riscv_arch;
extern const bfd_arch_info_type bfd_rs6000_arch;
extern const bfd_arch_info_type bfd_rl78_arch;
extern const bfd_arch_info_type bfd_rx_arch;
......@@ -717,8 +721,9 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_or1k_arch,
&bfd_pdp11_arch,
&bfd_powerpc_arch,
&bfd_rs6000_arch,
&bfd_riscv_arch,
&bfd_rl78_arch,
&bfd_rs6000_arch,
&bfd_rx_arch,
&bfd_s390_arch,
&bfd_score_arch,
......
......@@ -2295,6 +2295,9 @@ enum bfd_architecture
#define bfd_mach_cris_v0_v10 255
#define bfd_mach_cris_v32 32
#define bfd_mach_cris_v10_v32 1032
bfd_arch_riscv,
#define bfd_mach_riscv32 132
#define bfd_mach_riscv64 164
bfd_arch_rl78,
#define bfd_mach_rl78 0x75
bfd_arch_rx, /* Renesas RX. */
......@@ -4691,6 +4694,46 @@ number for the IN and OUT instructions */
number for the SBIC, SBIS, SBI and CBI instructions */
BFD_RELOC_AVR_PORT5,
/* RISC-V relocations. */
BFD_RELOC_RISCV_HI20,
BFD_RELOC_RISCV_PCREL_HI20,
BFD_RELOC_RISCV_PCREL_LO12_I,
BFD_RELOC_RISCV_PCREL_LO12_S,
BFD_RELOC_RISCV_LO12_I,
BFD_RELOC_RISCV_LO12_S,
BFD_RELOC_RISCV_GPREL12_I,
BFD_RELOC_RISCV_GPREL12_S,
BFD_RELOC_RISCV_TPREL_HI20,
BFD_RELOC_RISCV_TPREL_LO12_I,
BFD_RELOC_RISCV_TPREL_LO12_S,
BFD_RELOC_RISCV_TPREL_ADD,
BFD_RELOC_RISCV_CALL,
BFD_RELOC_RISCV_CALL_PLT,
BFD_RELOC_RISCV_ADD8,
BFD_RELOC_RISCV_ADD16,
BFD_RELOC_RISCV_ADD32,
BFD_RELOC_RISCV_ADD64,
BFD_RELOC_RISCV_SUB8,
BFD_RELOC_RISCV_SUB16,
BFD_RELOC_RISCV_SUB32,
BFD_RELOC_RISCV_SUB64,
BFD_RELOC_RISCV_GOT_HI20,
BFD_RELOC_RISCV_TLS_GOT_HI20,
BFD_RELOC_RISCV_TLS_GD_HI20,
BFD_RELOC_RISCV_JMP,
BFD_RELOC_RISCV_TLS_DTPMOD32,
BFD_RELOC_RISCV_TLS_DTPREL32,
BFD_RELOC_RISCV_TLS_DTPMOD64,
BFD_RELOC_RISCV_TLS_DTPREL64,
BFD_RELOC_RISCV_TLS_TPREL32,
BFD_RELOC_RISCV_TLS_TPREL64,
BFD_RELOC_RISCV_ALIGN,
BFD_RELOC_RISCV_RVC_BRANCH,
BFD_RELOC_RISCV_RVC_JUMP,
BFD_RELOC_RISCV_RVC_LUI,
BFD_RELOC_RISCV_GPREL_I,
BFD_RELOC_RISCV_GPREL_S,
/* Renesas RL78 Relocations. */
BFD_RELOC_RL78_NEG8,
BFD_RELOC_RL78_NEG16,
......
......@@ -122,6 +122,7 @@ or1k*|or1knd*) targ_archs=bfd_or1k_arch ;;
pdp11*) targ_archs=bfd_pdp11_arch ;;
pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
riscv*) targ_archs=bfd_riscv_arch ;;
rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
s390*) targ_archs=bfd_s390_arch ;;
sh*) targ_archs=bfd_sh_arch ;;
......@@ -1359,6 +1360,20 @@ case "${targ}" in
targ_selvecs="powerpc_pei_le_vec powerpc_pei_vec powerpc_pe_le_vec powerpc_pe_vec"
;;
#ifdef BFD64
riscv32-*-*)
targ_defvec=riscv_elf32_vec
targ_selvecs="riscv_elf32_vec"
want64=true
;;
riscv64-*-*)
targ_defvec=riscv_elf64_vec
targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
want64=true
;;
#endif
rl78-*-elf)
targ_defvec=rl78_elf32_vec
;;
......
......@@ -14475,6 +14475,8 @@ do
powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;;
powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;;
powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;;
riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
......
......@@ -606,6 +606,8 @@ do
powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;;
powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;;
powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;;
riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
......
/* BFD backend for RISC-V
Copyright 2011-2016 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
/* This routine is provided two arch_infos and returns an arch_info
that is compatible with both, or NULL if none exists. */
static const bfd_arch_info_type *
riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
{
if (a->arch != b->arch)
return NULL;
/* Machine compatibility is checked in
_bfd_riscv_elf_merge_private_bfd_data. */
return a;
}
#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
{ \
BITS_WORD, /* bits in a word */ \
BITS_ADDR, /* bits in an address */ \
8, /* 8 bits in a byte */ \
bfd_arch_riscv, \
NUMBER, \
"riscv", \
PRINT, \
3, \
DEFAULT, \
riscv_compatible, \
bfd_default_scan, \
bfd_arch_default_fill, \
NEXT, \
}
/* This enum must be kept in the same order as arch_info_struct. */
enum
{
I_riscv64,
I_riscv32
};
#define NN(index) (&arch_info_struct[(index) + 1])
/* This array must be kept in the same order as the anonymous enum above,
and each entry except the last should end with NN (my enum value). */
static const bfd_arch_info_type arch_info_struct[] =
{
N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)),
N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0)
};
/* The default architecture is riscv:rv64. */
const bfd_arch_info_type bfd_riscv_arch =
N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
......@@ -477,6 +477,7 @@ enum elf_target_id
XGATE_ELF_DATA,
TILEGX_ELF_DATA,
TILEPRO_ELF_DATA,
RISCV_ELF_DATA,
GENERIC_ELF_DATA
};
......
This diff is collapsed.
This diff is collapsed.
/* RISC-V ELF specific backend routines.
Copyright 2011-2016 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "elf/common.h"
#include "elf/internal.h"
extern reloc_howto_type *
riscv_reloc_name_lookup (bfd *, const char *);
extern reloc_howto_type *
riscv_reloc_type_lookup (bfd *, bfd_reloc_code_real_type);
extern reloc_howto_type *
riscv_elf_rtype_to_howto (unsigned int r_type);
......@@ -2166,6 +2166,44 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_AVR_LDS_STS_16",
"BFD_RELOC_AVR_PORT6",
"BFD_RELOC_AVR_PORT5",
"BFD_RELOC_RISCV_HI20",
"BFD_RELOC_RISCV_PCREL_HI20",
"BFD_RELOC_RISCV_PCREL_LO12_I",
"BFD_RELOC_RISCV_PCREL_LO12_S",
"BFD_RELOC_RISCV_LO12_I",
"BFD_RELOC_RISCV_LO12_S",
"BFD_RELOC_RISCV_GPREL12_I",
"BFD_RELOC_RISCV_GPREL12_S",
"BFD_RELOC_RISCV_TPREL_HI20",
"BFD_RELOC_RISCV_TPREL_LO12_I",
"BFD_RELOC_RISCV_TPREL_LO12_S",
"BFD_RELOC_RISCV_TPREL_ADD",
"BFD_RELOC_RISCV_CALL",
"BFD_RELOC_RISCV_CALL_PLT",
"BFD_RELOC_RISCV_ADD8",
"BFD_RELOC_RISCV_ADD16",
"BFD_RELOC_RISCV_ADD32",
"BFD_RELOC_RISCV_ADD64",
"BFD_RELOC_RISCV_SUB8",
"BFD_RELOC_RISCV_SUB16",
"BFD_RELOC_RISCV_SUB32",
"BFD_RELOC_RISCV_SUB64",
"BFD_RELOC_RISCV_GOT_HI20",
"BFD_RELOC_RISCV_TLS_GOT_HI20",
"BFD_RELOC_RISCV_TLS_GD_HI20",
"BFD_RELOC_RISCV_JMP",
"BFD_RELOC_RISCV_TLS_DTPMOD32",
"BFD_RELOC_RISCV_TLS_DTPREL32",
"BFD_RELOC_RISCV_TLS_DTPMOD64",
"BFD_RELOC_RISCV_TLS_DTPREL64",
"BFD_RELOC_RISCV_TLS_TPREL32",
"BFD_RELOC_RISCV_TLS_TPREL64",
"BFD_RELOC_RISCV_ALIGN",
"BFD_RELOC_RISCV_RVC_BRANCH",
"BFD_RELOC_RISCV_RVC_JUMP",
"BFD_RELOC_RISCV_RVC_LUI",
"BFD_RELOC_RISCV_GPREL_I",
"BFD_RELOC_RISCV_GPREL_S",
"BFD_RELOC_RL78_NEG8",
"BFD_RELOC_RL78_NEG16",
"BFD_RELOC_RL78_NEG24",
......
......@@ -5047,6 +5047,86 @@ ENUM
ENUMDOC
This is a 5 bit reloc for the AVR that stores an I/O register
number for the SBIC, SBIS, SBI and CBI instructions
ENUM
BFD_RELOC_RISCV_HI20
ENUMX
BFD_RELOC_RISCV_PCREL_HI20
ENUMX
BFD_RELOC_RISCV_PCREL_LO12_I
ENUMX
BFD_RELOC_RISCV_PCREL_LO12_S
ENUMX
BFD_RELOC_RISCV_LO12_I
ENUMX
BFD_RELOC_RISCV_LO12_S
ENUMX
BFD_RELOC_RISCV_GPREL12_I
ENUMX
BFD_RELOC_RISCV_GPREL12_S
ENUMX
BFD_RELOC_RISCV_TPREL_HI20
ENUMX
BFD_RELOC_RISCV_TPREL_LO12_I
ENUMX
BFD_RELOC_RISCV_TPREL_LO12_S
ENUMX
BFD_RELOC_RISCV_TPREL_ADD
ENUMX
BFD_RELOC_RISCV_CALL
ENUMX
BFD_RELOC_RISCV_CALL_PLT
ENUMX
BFD_RELOC_RISCV_ADD8
ENUMX
BFD_RELOC_RISCV_ADD16
ENUMX
BFD_RELOC_RISCV_ADD32
ENUMX
BFD_RELOC_RISCV_ADD64
ENUMX
BFD_RELOC_RISCV_SUB8
ENUMX
BFD_RELOC_RISCV_SUB16
ENUMX
BFD_RELOC_RISCV_SUB32
ENUMX
BFD_RELOC_RISCV_SUB64
ENUMX
BFD_RELOC_RISCV_GOT_HI20
ENUMX
BFD_RELOC_RISCV_TLS_GOT_HI20
ENUMX
BFD_RELOC_RISCV_TLS_GD_HI20
ENUMX
BFD_RELOC_RISCV_JMP
ENUMX
BFD_RELOC_RISCV_TLS_DTPMOD32
ENUMX
BFD_RELOC_RISCV_TLS_DTPREL32
ENUMX
BFD_RELOC_RISCV_TLS_DTPMOD64
ENUMX
BFD_RELOC_RISCV_TLS_DTPREL64
ENUMX
BFD_RELOC_RISCV_TLS_TPREL32
ENUMX
BFD_RELOC_RISCV_TLS_TPREL64
ENUMX
BFD_RELOC_RISCV_ALIGN
ENUMX
BFD_RELOC_RISCV_RVC_BRANCH
ENUMX
BFD_RELOC_RISCV_RVC_JUMP
ENUMX
BFD_RELOC_RISCV_RVC_LUI
ENUMX
BFD_RELOC_RISCV_GPREL_I
ENUMX
BFD_RELOC_RISCV_GPREL_S
ENUMDOC
RISC-V relocations.
ENUM
BFD_RELOC_RL78_NEG8
ENUMX
......
......@@ -799,6 +799,8 @@ extern const bfd_target powerpc_pe_le_vec;
extern const bfd_target powerpc_pei_vec;
extern const bfd_target powerpc_pei_le_vec;
extern const bfd_target powerpc_xcoff_vec;
extern const bfd_target riscv_elf32_vec;
extern const bfd_target riscv_elf64_vec;
extern const bfd_target rl78_elf32_vec;
extern const bfd_target rs6000_xcoff64_vec;
extern const bfd_target rs6000_xcoff64_aix_vec;
......@@ -1303,6 +1305,10 @@ static const bfd_target * const _bfd_target_vector[] =
&powerpc_xcoff_vec,
#endif
&riscv_elf32_vec,
#ifdef BFD64
&riscv_elf64_vec,
#endif
&rl78_elf32_vec,
#ifdef BFD64
......
2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
Andrew Waterman <andrew@sifive.com>
Add support for RISC-V architecture.
* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.
2016-10-17 Nick Clifton <nickc@redhat.com>
* readelf.c (apply_relocations): Fail if the symbol table section
......
......@@ -124,6 +124,7 @@
#include "elf/metag.h"
#include "elf/microblaze.h"
#include "elf/mips.h"
#include "elf/riscv.h"