Commit e407c74b authored by Nick Clifton's avatar Nick Clifton
Browse files

* archures.c: Add support for MIPS r5900

	* bfd-in2.h: Add support for MIPS r5900
	* config.bfd: Add support for Sony Playstation 2
	* cpu-mips.c: Add support for MIPS r5900
	* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000)

	* config/tc-mips.c: Add support for MIPS r5900
	Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq.
	* config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot.
	* config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900.
	* config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
	* config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900.
	* configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu).

	* config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900.

	* elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software.
	* opcode/mips.h: Add support for r5900 instructions including lq and sq.

	* configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk).
	* emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32.
	* emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32.
	* Makefile.am: Add linker scripts for Sony Playstation 2 ELF files.

	* opcodes/mips-dis.c: Add names for CP0 registers of r5900.
	* opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq.

	* opcodes/mips-opc.c: Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
parent fb098a1e
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
* archures.c (bfd_mach_mips5900): Define.
* bfd-in2.h: Regenerate.
* config.bfd: Add mips64-ps2-elf and mips-ps2-elf targets.
* cpu-mips.c: Add support for MIPS r5900.
* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000).
2013-01-03 Nickolai Zeldovich <nickolai@csail.mit.edu>
Nick Clifton <nickc@redhat.com>
......
/* BFD library support routines for architectures.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
2012 Free Software Foundation, Inc.
2012, 2013 Free Software Foundation, Inc.
Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
......@@ -161,6 +161,7 @@ DESCRIPTION
.#define bfd_mach_mips5000 5000
.#define bfd_mach_mips5400 5400
.#define bfd_mach_mips5500 5500
.#define bfd_mach_mips5900 5900
.#define bfd_mach_mips6000 6000
.#define bfd_mach_mips7000 7000
.#define bfd_mach_mips8000 8000
......
......@@ -1892,6 +1892,7 @@ enum bfd_architecture
#define bfd_mach_mips5000 5000
#define bfd_mach_mips5400 5400
#define bfd_mach_mips5500 5500
#define bfd_mach_mips5900 5900
#define bfd_mach_mips6000 6000
#define bfd_mach_mips7000 7000
#define bfd_mach_mips8000 8000
......
......@@ -974,7 +974,16 @@ case "${targ}" in
targ_selvecs="bfd_elf32_nlittlemips_vec bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
want64=true
;;
mips64*-ps2-elf*)
targ_defvec=bfd_elf32_nlittlemips_vec
targ_selvecs="bfd_elf32_nlittlemips_vec bfd_elf32_nbigmips_vec bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
want64=true
;;
#endif
mips*-ps2-elf*)
targ_defvec=bfd_elf32_littlemips_vec
targ_selvecs="bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
;;
mips*-*-irix5*)
targ_defvec=bfd_elf32_bigmips_vec
targ_selvecs="bfd_elf32_littlemips_vec ecoff_big_vec ecoff_little_vec"
......
/* bfd back-end for mips support
Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
2002, 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
2002, 2003, 2004, 2005, 2007, 2008, 2009, 2013
Free Software Foundation, Inc.
Written by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
......@@ -75,6 +76,7 @@ enum
I_mips5000,
I_mips5400,
I_mips5500,
I_mips5900,
I_mips6000,
I_mips7000,
I_mips8000,
......@@ -118,6 +120,7 @@ static const bfd_arch_info_type arch_info_struct[] =
N (64, 64, bfd_mach_mips5000, "mips:5000", FALSE, NN(I_mips5000)),
N (64, 64, bfd_mach_mips5400, "mips:5400", FALSE, NN(I_mips5400)),
N (64, 64, bfd_mach_mips5500, "mips:5500", FALSE, NN(I_mips5500)),
N (64, 32, bfd_mach_mips5900, "mips:5900", FALSE, NN(I_mips5900)),
N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
......
/* MIPS-specific support for ELF
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
Free Software Foundation, Inc.
Most of the information added by Ian Lance Taylor, Cygnus Support,
......@@ -6294,6 +6294,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_5500:
return bfd_mach_mips5500;
case E_MIPS_MACH_5900:
return bfd_mach_mips5900;
case E_MIPS_MACH_9000:
return bfd_mach_mips9000;
......@@ -11026,6 +11029,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
break;
case bfd_mach_mips5900:
val = E_MIPS_ARCH_3 | E_MIPS_MACH_5900;
break;
case bfd_mach_mips9000:
val = E_MIPS_ARCH_4 | E_MIPS_MACH_9000;
break;
......@@ -13708,6 +13715,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
{ bfd_mach_mips4300, bfd_mach_mips4000 },
{ bfd_mach_mips4100, bfd_mach_mips4000 },
{ bfd_mach_mips4010, bfd_mach_mips4000 },
{ bfd_mach_mips5900, bfd_mach_mips4000 },
/* MIPS32 extensions. */
{ bfd_mach_mipsisa32r2, bfd_mach_mipsisa32 },
......
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c: Add support for MIPS r5900.
Add M_LQ_AB and M_SQ_AB to support large values for instructions
lq and sq.
(can_swap_branch_p, get_append_method): Detect some conditional
short loops to fix a bug on the r5900 by NOP in the branch delay
slot.
(M_MUL): Support 3 operands in multu on r5900.
(M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
(s_mipsset): Force 32 bit floating point on r5900.
(mips_ip): Check parameter range of instructions mfps and mtps on
r5900.
* configure.in: Detect CPU type when target string contains r5900
(e.g. mips64r5900el-linux-gnu).
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
* as.c (parse_args): Update copyright year to 2013.
......
/* tc-mips.c -- assemble code for a MIPS chip.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
Free Software Foundation, Inc.
Contributed by the OSF and Ralph Campbell.
Written by Keith Knowles and Ralph Campbell, working independently.
......@@ -171,6 +171,10 @@ struct mips_cl_insn
 
/* True if this instruction is complete. */
unsigned int complete_p : 1;
/* True if this instruction is cleared from history by unconditional
branch. */
unsigned int cleared_p : 1;
};
 
/* The ABI to use. */
......@@ -518,6 +522,7 @@ static int mips_32bitmode = 0;
|| mips_opts.isa == ISA_MIPS64 \
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.arch == CPU_R4010 \
|| mips_opts.arch == CPU_R5900 \
|| mips_opts.arch == CPU_R10000 \
|| mips_opts.arch == CPU_R12000 \
|| mips_opts.arch == CPU_R14000 \
......@@ -535,6 +540,7 @@ static int mips_32bitmode = 0;
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
|| mips_opts.arch == CPU_R3900 \
|| mips_opts.arch == CPU_R5900 \
|| mips_opts.micromips \
)
 
......@@ -1679,6 +1685,7 @@ create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
insn->noreorder_p = (mips_opts.noreorder > 0);
insn->mips16_absolute_jump_p = 0;
insn->complete_p = 0;
insn->cleared_p = 0;
}
 
/* Record the current MIPS16/microMIPS mode in now_seg. */
......@@ -3735,10 +3742,13 @@ fix_loongson2f (struct mips_cl_insn * ip)
 
/* IP is a branch that has a delay slot, and we need to fill it
automatically. Return true if we can do that by swapping IP
with the previous instruction. */
with the previous instruction.
ADDRESS_EXPR is an operand of the instruction to be used with
RELOC_TYPE. */
 
static bfd_boolean
can_swap_branch_p (struct mips_cl_insn *ip)
can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
bfd_reloc_code_real_type *reloc_type)
{
unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
......@@ -3857,13 +3867,64 @@ can_swap_branch_p (struct mips_cl_insn *ip)
&& insn_length (history) != 4)
return FALSE;
 
/* On R5900 short loops need to be fixed by inserting a nop in
the branch delay slots.
A short loop can be terminated too early. */
if (mips_opts.arch == CPU_R5900
/* Check if instruction has a parameter, ignore "j $31". */
&& (address_expr != NULL)
/* Parameter must be 16 bit. */
&& (*reloc_type == BFD_RELOC_16_PCREL_S2)
/* Branch to same segment. */
&& (S_GET_SEGMENT(address_expr->X_add_symbol) == now_seg)
/* Branch to same code fragment. */
&& (symbol_get_frag(address_expr->X_add_symbol) == frag_now)
/* Can only calculate branch offset if value is known. */
&& symbol_constant_p(address_expr->X_add_symbol)
/* Check if branch is really conditional. */
&& !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
|| (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
|| (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
{
int distance;
/* Check if loop is shorter than 6 instructions including
branch and delay slot. */
distance = frag_now_fix() - S_GET_VALUE(address_expr->X_add_symbol);
if (distance <= 20)
{
int i;
int rv;
rv = FALSE;
/* When the loop includes branches or jumps,
it is not a short loop. */
for (i = 0; i < (distance / 4); i++)
{
if ((history[i].cleared_p)
|| delayed_branch_p(&history[i]))
{
rv = TRUE;
break;
}
}
if (rv == FALSE)
{
/* Insert nop after branch to fix short loop. */
return FALSE;
}
}
}
return TRUE;
}
 
/* Decide how we should add IP to the instruction stream. */
/* Decide how we should add IP to the instruction stream.
ADDRESS_EXPR is an operand of the instruction to be used with
RELOC_TYPE. */
 
static enum append_method
get_append_method (struct mips_cl_insn *ip)
get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
bfd_reloc_code_real_type *reloc_type)
{
unsigned long pinfo;
 
......@@ -3879,7 +3940,8 @@ get_append_method (struct mips_cl_insn *ip)
/* Otherwise, it's our responsibility to fill branch delay slots. */
if (delayed_branch_p (ip))
{
if (!branch_likely_p (ip) && can_swap_branch_p (ip))
if (!branch_likely_p (ip)
&& can_swap_branch_p (ip, address_expr, reloc_type))
return APPEND_SWAP;
 
pinfo = ip->insn_mo->pinfo;
......@@ -4260,7 +4322,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
}
}
 
method = get_append_method (ip);
method = get_append_method (ip, address_expr, reloc_type);
branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
 
#ifdef OBJ_ELF
......@@ -4578,8 +4640,17 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
/* If we have just completed an unconditional branch, clear the history. */
if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
|| (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
{
unsigned int i;
mips_no_prev_insn ();
 
for (i = 0; i < ARRAY_SIZE (history); i++)
{
history[i].cleared_p = 1;
}
}
/* We need to emit a label at the end of branch-likely macros. */
if (emit_branch_likely_macro)
{
......@@ -4591,7 +4662,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
mips_clear_insn_labels ();
}
 
/* Forget that there was any previous instruction or label. */
/* Forget that there was any previous instruction or label.
When BRANCH is true, the branch history is also flushed. */
 
static void
mips_no_prev_insn (void)
......@@ -8858,7 +8930,8 @@ macro (struct mips_cl_insn *ip)
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
&& (mips_opts.arch != CPU_R5900))
{
macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
......@@ -8881,7 +8954,8 @@ macro (struct mips_cl_insn *ip)
macro_build_lui (&offset_expr, AT);
}
 
if (mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
&& (mips_opts.arch != CPU_R5900))
{
macro_build (&offset_expr, "ldc1", "T,o(b)",
treg, BFD_RELOC_LO16, AT);
......@@ -8898,7 +8972,8 @@ macro (struct mips_cl_insn *ip)
r = BFD_RELOC_LO16;
dob:
gas_assert (!mips_opts.micromips);
gas_assert (mips_opts.isa == ISA_MIPS1);
gas_assert ((mips_opts.isa == ISA_MIPS1)
|| (mips_opts.arch == CPU_R5900));
macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg, r, breg);
/* FIXME: A possible overflow which I don't know how to deal
......@@ -8936,7 +9011,7 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
fmt = "T,o(b)";
if (mips_opts.isa != ISA_MIPS1)
if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
{
s = "ldc1";
goto ld_st;
......@@ -8949,7 +9024,7 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
fmt = "T,o(b)";
if (mips_opts.isa != ISA_MIPS1)
if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900))
{
s = "sdc1";
goto ld_st;
......@@ -8957,6 +9032,16 @@ macro (struct mips_cl_insn *ip)
s = "swc1";
goto ldd_std;
 
case M_LQ_AB:
fmt = "t,o(b)";
s = "lq";
goto ld;
case M_SQ_AB:
fmt = "t,o(b)";
s = "sq";
goto ld_st;
case M_LD_AB:
fmt = "t,o(b)";
if (HAVE_64BIT_GPRS)
......@@ -9269,8 +9354,15 @@ macro (struct mips_cl_insn *ip)
case M_DMUL:
dbl = 1;
case M_MUL:
if (mips_opts.arch == CPU_R5900)
{
macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", dreg, sreg, treg);
}
else
{
macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
macro_build (NULL, "mflo", MFHL_FMT, dreg);
}
break;
 
case M_DMUL_I:
......@@ -9833,7 +9925,7 @@ macro (struct mips_cl_insn *ip)
case M_TRUNCWS:
case M_TRUNCWD:
gas_assert (!mips_opts.micromips);
gas_assert (mips_opts.isa == ISA_MIPS1);
gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900));
used_at = 1;
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
......@@ -10638,7 +10730,7 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
/* Let a macro pass, we'll catch it later when it is expanded. */
return 1;
 
if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || (mips_opts.arch == CPU_R5900))
{
/* Allow odd registers for single-precision ops. */
switch (insn->pinfo & (FP_S | FP_D))
......@@ -11789,6 +11881,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
as_warn (_("Invalid performance register (%lu)"),
(unsigned long) imm_expr.X_add_number);
if (imm_expr.X_add_number != 0 && mips_opts.arch == CPU_R5900
&& (!strcmp(insn->name,"mfps") || !strcmp(insn->name,"mtps")))
as_warn (_("Invalid performance register (%lu)"),
(unsigned long) imm_expr.X_add_number);
INSERT_OPERAND (0, PERFREG, *ip, imm_expr.X_add_number);
imm_expr.X_op = O_absent;
s = expr_end;
......@@ -16380,7 +16476,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
case ISA_MIPS64:
case ISA_MIPS64R2:
mips_opts.gp32 = 0;
if (mips_opts.arch == CPU_R5900)
{
mips_opts.fp32 = 1;
}
else
{
mips_opts.fp32 = 0;
}
break;
default:
as_bad (_("unknown ISA level %s"), name + 4);
......@@ -19082,6 +19185,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "r4600", 0, ISA_MIPS3, CPU_R4600 },
{ "orion", 0, ISA_MIPS3, CPU_R4600 },
{ "r4650", 0, ISA_MIPS3, CPU_R4650 },
{ "r5900", 0, ISA_MIPS3, CPU_R5900 },
/* ST Microelectronics Loongson 2E and 2F cores */
{ "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
{ "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
......
......@@ -12060,6 +12060,9 @@ _ACEOF
mips64* | mipsisa64* | mipsisa32*)
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
;;
mips*)
mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
;;
*)
as_fn_error "$target_cpu isn't a supported MIPS CPU name" "$LINENO" 5
;;
......
......@@ -3,7 +3,7 @@ dnl
dnl And be careful when changing it! If you must add tests with square
dnl brackets, be sure changequote invocations surround it.
dnl
dnl Copyright 2012 Free Software Foundation
dnl Copyright 2012, 2013 Free Software Foundation
dnl
dnl This file is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
......@@ -245,6 +245,11 @@ changequote([,])dnl
mips64* | mipsisa64* | mipsisa32*)
changequote(,)dnl
mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'`
changequote([,])dnl
;;
mips*)
changequote(,)dnl
mips_cpu=`echo $target_cpu | sed -e 's/^mips//' -e 's/el$//'`
changequote([,])dnl
;;
*)
......
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-full.s: New test.
* gas/mips/r5900-full.d: Expected disassembly.
* gas/mips/r5900.s: New test.
* gas/mips/r5900.d: Expected disassembly.
* gas/mips/mips.exp: Run new tests.
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/int-insns.d: Update.
......
# Copyright 2012
# Copyright 2012, 2013
# Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
......@@ -88,6 +88,9 @@
# The architecture provides 32- or 64-bit General Purpose
# Registers.
#
# singlefloat
# The CPU is 64 bit, but only supports 32 bit FPU.
#
# as_flags: The assembler flags used when assembling tests for this
# architecture.
#
......@@ -460,6 +463,9 @@ mips_arch_create octeon2 64 octeonp {} \
{ }
mips_arch_create xlr 64 mips64 {} \
{ -march=xlr -mtune=xlr } { -mmips:xlr }
mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat } \
{ -march=r5900 -mtune=r5900 } { -mmips:5900 } \
{ mipsr5900el-*-* mips64r5900el-*-* }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
......@@ -563,13 +569,13 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "24k-triple-stores-3" \
[mips_arch_list_matching mips2]
run_dump_test_arches "24k-triple-stores-4" \
[mips_arch_list_matching mips2]
[mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-5" \
[mips_arch_list_matching mips1]
run_dump_test_arches "24k-triple-stores-6" \
[mips_arch_list_matching mips2]
[mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-7" \
[mips_arch_list_matching mips2]
[mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "24k-triple-stores-8" \
[mips_arch_list_matching mips1]
run_dump_test_arches "24k-triple-stores-9" \
......@@ -618,18 +624,18 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd" [mips_arch_list_matching mips1]
run_dump_test_arches "sd-forward" \
[mips_arch_list_matching mips1]
run_dump_test_arches "l_d" [mips_arch_list_matching mips1]
run_dump_test_arches "l_d" [mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "l_d-forward" \
[mips_arch_list_matching mips1]
run_dump_test_arches "s_d" [mips_arch_list_matching mips1]
[mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "s_d" [mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "s_d-forward" \
[mips_arch_list_matching mips1]
run_dump_test_arches "ldc1" [mips_arch_list_matching mips2]
[mips_arch_list_matching mips1 !singlefloat]
run_dump_test_arches "ldc1" [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "ldc1-forward" \
[mips_arch_list_matching mips2]
run_dump_test_arches "sdc1" [mips_arch_list_matching mips2]
[mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "sdc1" [mips_arch_list_matching mips2 !singlefloat]
run_dump_test_arches "sdc1-forward" \
[mips_arch_list_matching mips2]
[mips_arch_list_matching mips2 !singlefloat]
if $has_newabi {
run_dump_test_arches "ld-n32" \
[mips_arch_list_matching mips3]
......@@ -640,21 +646,21 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd-forward-n32" \
[mips_arch_list_matching mips3]
run_dump_test_arches "l_d-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "l_d-forward-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-forward-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-forward-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-forward-n32" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ld-n64" \
[mips_arch_list_matching mips3]
run_dump_test_arches "ld-forward-n64" \
......@@ -664,21 +670,21 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "sd-forward-n64" \
[mips_arch_list_matching mips3]
run_dump_test_arches "l_d-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "l_d-forward-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "s_d-forward-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "ldc1-forward-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
run_dump_test_arches "sdc1-forward-n64" \
[mips_arch_list_matching mips3]
[mips_arch_list_matching mips3 !singlefloat]
}
}
if $elf { run_dump_test "ld-svr4pic" }
......@@ -876,7 +882,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips-abi32-pic2"
run_dump_test "elf${el}-rel"
run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64]
run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64 !singlefloat]
run_dump_test "e32${el}-rel2"
run_dump_test "elf${el}-rel3"
run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
......@@ -1096,10 +1102,10 @@ if { [istarget mips*-*-vxworks*] } {
run_list_test_arches "mips-hard-float-flag" \
"-32 -msoft-float -mhard-float" \
[mips_arch_list_matching mips1]
[mips_arch_list_matching mips1 !singlefloat]
run_list_test_arches "mips-double-float-flag" \
"-32 -msingle-float -mdouble-float" \
[mips_arch_list_matching mips1]
[mips_arch_list_matching mips1 !singlefloat]
run_dump_test "mips16-vis-1"
run_dump_test "call-nonpic-1"
......@@ -1148,4 +1154,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "lui" [mips_arch_list_matching mips1]
run_list_test_arches "lui-1" "-32" [mips_arch_list_matching mips1]
run_list_test_arches "lui-2" "-32" [mips_arch_list_matching mips1]
run_dump_test "r5900"
run_dump_test "r5900-full"
}
#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
#name: Full MIPS R5900
#as: -march=r5900 -mtune=r5900
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 001f0020 add \$0,\$0,\$31
[0-9a-f]+ <[^>]*> 01430820 add \$1,\$10,\$3
[0-9a-f]+ <[^>]*> 03e0f820 add \$31,\$31,\$0
[0-9a-f]+ <[^>]*> 201f0000 addi \$31,\$0,0
[0-9a-f]+ <[^>]*> 21410003 addi \$1,\$10,3
[0-9a-f]+ <[^>]*> 23e0ffff addi \$0,\$31,-1
[0-9a-f]+ <[^>]*> 241f0000 li \$31,0
[0-9a-f]+ <[^>]*> 25410003 addiu \$1,\$10,3
[0-9a-f]+ <[^>]*> 241fffff li \$31,-1
[0-9a-f]+ <[^>]*> 001f0024 and \$0,\$0,\$31
[0