1. 27 Jan, 2020 6 commits
  2. 23 Jan, 2020 5 commits
    • Hannes Domani's avatar
      Cache the text section offset of shared libraries · c162ed3e
      Hannes Domani authored
      Each time a dll is loaded, update_solib_list is called.
      This in turn calls deep down xfer_partial -> windows_xfer_shared_libraries,
      which calls windows_xfer_shared_library for each loaded dll,
      and pe_text_section_offset reads the dll for the text section offset.
      
      Also if the data provided by xfer_partial is bigger than 4K,
      then all of this is done for each 4K chunk (see target_read_alloc_1).
      
      Caching of the text section offset improves the startup time of
      an application with >300 dynamically loaded plugins from 2m10s to 10s.
      And the shutdown time improves from 2m to 2s.
      
      gdb/ChangeLog:
      
      2020-01-23  Hannes Domani  <ssbssa@yahoo.de>
      
      	* i386-cygwin-tdep.c (core_process_module_section): Update.
      	* windows-nat.c (struct lm_info_windows): Add text_offset.
      	(windows_xfer_shared_libraries): Update.
      	* windows-tdep.c (windows_xfer_shared_library):
      	Add text_offset_cached argument.
      	* windows-tdep.h (windows_xfer_shared_library): Update.
      c162ed3e
    • Nick Clifton's avatar
    • Alan Modra's avatar
      PR25444, Floating point exception in _bfd_elf_compute_section_file_positions · 67641dd3
      Alan Modra authored
      	PR 25444
      	* elf.c (assign_file_positions_for_load_sections): Avoid divide
      	by zero when p_align is zero.
      67641dd3
    • Jim Wilson's avatar
      RISC-V: Change -march parsing. · 403d1bd9
      Jim Wilson authored
      	bfd/
      	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
      	* bfd/elfnn-riscv.c (riscv_skip_prefix): New.
      	(riscv_prefix_cmp): Likewise.
      	(riscv_non_std_ext_p): Deleted.
      	(riscv_std_sv_ext_p): Likewise.
      	(riscv_non_std_sv_ext_p): Likewise.
      	(riscv_merge_non_std_and_sv_ext): Rename to...
      	(riscv_merge_multi_letter_ext): and modified to use riscv_prefix_cmp.
      	(riscv_merge_arch_attr_info): Replace 3 calls to
      	riscv_merge_non_std_and_sv_ext with single call to
      	riscv_merge_multi_letter_ext.
      	* bfd/elfxx-riscv.c (riscv_parse_std_ext): Break if we
      	encounter a 'z' prefix.
      	(riscv_get_prefix_class): New function, return prefix class based
      	on first few characters of input string.
      	(riscv_parse_config): New structure to factor out minor differences
      	in extension class parsing behaviour.
      	(riscv_parse_sv_or_non_std_ext): Rename to...
      	(riscv_parse_prefixed_ext): and parameterise with
      	riscv_parse_config.
      	(riscv_std_z_ext_strtab, riscv_std_s_ext_strtab): New.
      	(riscv_multi_letter_ext_valid_p): New.
      	(riscv_ext_x_valid_p, riscv_ext_z_valid_p, riscv_ext_s_valid_p): New.
      	(riscv_parse_subset): Delegate all non-single-letter parsing work
      	to riscv_parse_prefixed_ext.
      	* bfd/elfxx-riscv.h (riscv_isa_ext_class): New type.
      	(riscv_get_prefix_class): Declare.
      
      	gas/
      	2020-01-22  Maxim Blinov  <maxim.blinov@embecosm.com>
      	* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
      	s exts must be known, so rename *ok* to *fail*.
      	* testsuite/gas/riscv/march-ok-sx.d: Likewise.
      	* testsuite/gas/riscv/march-ok-s-with-version: Likewise.
      	* testsuite/gas/riscv/march-fail-s.l: Expected error messages for
      	above change.
      	* testsuite/gas/riscv/march-fail-sx.l: Likewise.
      	* testsuite/gas/riscv/march-fail-sx-with-version.l: Likewise.
      
      Change-Id: Ic4d91a13d055a10d30ab28752a380a669b59f29c
      403d1bd9
    • GDB Administrator's avatar
      Automatic date update in version.in · 34013474
      GDB Administrator authored
      34013474
  3. 22 Jan, 2020 9 commits
    • Jozef Lawrynowicz's avatar
      MSP430: Fix simulator execution of RRUX instruction · b7dcc42d
      Jozef Lawrynowicz authored
      The MSP430X RRUX instruction (unsigned right shift) is synthesized as
      the RRC (rotate right through carry) instruction, but with the ZC
      (zero carry) bit of the opcode extention word set.
      
      Ensure the carry flag is ignored when the ZC bit is set.
      
      sim/msp430/ChangeLog:
      
      2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
      
      	* msp430-sim.c (msp430_step_once): Ignore the carry flag when executing
      	an RRC instruction, if the ZC bit of the extension word is set.
      
      sim/testsuite/sim/msp430/ChangeLog:
      
      2020-01-22  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
      
      	* rrux.s: New test.
      b7dcc42d
    • H.J. Lu's avatar
      x86: Always disallow double word suffix with word general register · be4c5e58
      H.J. Lu authored
      In 64-bit mode, double word suffix in mnemonic with word general register
      is disallowed.  Otherwise, assembler gives a warning:
      
      $ cat /tmp/x.s
      	movl	%ax, %bx
      	movl	%ds, %ax
      	movl	%ax, %cs
      $ gcc -c /tmp/x.s
      /tmp/x.s: Assembler messages:
      /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
      /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
      /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
      $ gcc -c /tmp/x.s -m32
      /tmp/x.s: Assembler messages:
      /tmp/x.s: Assembler messages:
      /tmp/x.s:1: Warning: using `%ebx' instead of `%bx' due to `l' suffix
      /tmp/x.s:1: Warning: using `%eax' instead of `%ax' due to `l' suffix
      /tmp/x.s:2: Warning: using `%eax' instead of `%ax' due to `l' suffix
      /tmp/x.s:3: Warning: using `%eax' instead of `%ax' due to `l' suffix
      
      This patch makes it a hard error in all modes.  Now we get:
      
      $ gcc -c /tmp/x.s -m32
      /tmp/x.s: Assembler messages:
      /tmp/x.s:1: Error: incorrect register `%bx' used with `l' suffix
      /tmp/x.s:2: Error: incorrect register `%ax' used with `l' suffix
      /tmp/x.s:3: Error: incorrect register `%ax' used with `l' suffix
      
      	PR gas/25438
      	* config/tc-i386.c (check_long_reg): Always disallow double word
      	suffix in mnemonic with word general register.
      	* testsuite/gas/i386/general.s: Replace word general register
      	with double word general register for movl.
      	* testsuite/gas/i386/inval.s: Add tests for movl with word general
      	register.
      	* testsuite/gas/i386/general.l: Updated.
      	* testsuite/gas/i386/inval.l: Likewise.
      be4c5e58
    • H.J. Lu's avatar
      x86-64: Skip GNU2 TLS tests only without compiler support · 6a462ad4
      H.J. Lu authored
      After fixing:
      
      https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93319
      https://sourceware.org/bugzilla/show_bug.cgi?id=25416
      
      -mtls-dialect=gnu2 is working for x32 with GCC 10.  Skip GNU2 TLS tests
      only if compiler doesn't support it.
      
      	PR ld/25416
      	* testsuite/ld-x86-64/tls.exp: Skip GNU2 TLS tests only without
      	compiler support.
      6a462ad4
    • Alan Modra's avatar
      PowerPC64 tls_get_addr_desc static support · a804e476
      Alan Modra authored
      This provides a linker generated __tls_get_addr_desc wrapper function
      preserving registers around a __tls_get_addr call.  The idea being to
      support __tls_get_addr_desc without requiring a glibc update.
      
      bfd/
      	* elf64-ppc.c (struct ppc_link_hash_table): Add tga_group.
      	(ppc64_elf_archive_symbol_lookup): Extract __tls_get_addr_opt for
      	__tls_get_addr_desc.
      	(ppc64_elf_size_stubs): Add section for linker generated
      	__tls_get_addr_desc wrapper function.  Loop at least once if
      	generating this function.
      	(emit_tga_desc, emit_tga_desc_eh_frame): New functions.
      	(ppc64_elf_build_stubs): Generate __tls_get_addr_desc.
      ld/
      	* testsuite/ld-powerpc/tlsdesc3.d,
      	* testsuite/ld-powerpc/tlsdesc3.wf,
      	* testsuite/ld-powerpc/tlsdesc4.d,
      	* testsuite/ld-powerpc/tlsdesc4.s,
      	* testsuite/ld-powerpc/tlsdesc4.wf: New tests.
      	* testsuite/ld-powerpc/powerpc.exp: Run them.
      a804e476
    • Alan Modra's avatar
      PowerPC64 __tls_get_addr_desc · 9e7028aa
      Alan Modra authored
      This implements register saving and restoring in the __tls_get_addr
      call stub, so that when glibc supports the optimized tls call stub gcc
      can generate code that assumes only r0, r12 and of course r3 are
      changed on a __tls_get_addr call.  When gcc expects __tls_get_addr
      calls to preserve registers the call will be to __tls_get_addr_desc,
      which will be translated by the linker to a call to __tls_get_addr_opt.
      
      bfd/
      	* elf64-ppc.h (struct ppc64_elf_params): Add no_tls_get_addr_regsave.
      	* elf64-ppc.c (struct ppc_link_hash_table): Add tga_desc and
      	tga_desc_fd.
      	(is_tls_get_addr): Match tga_desc and tga_desc_df too.
      	(STDU_R1_0R1, ADDI_R1_R1): Define.
      	(tls_get_addr_prologue, tls_get_addr_epilogue): New functions.
      	(ppc64_elf_tls_setup): Set up tga_desc and tga_desc_fd.  Indirect
      	tga_desc_fd to opt_fd, and tga_desc to opt.  Set
      	no_tls_get_addr_regsave.
      	(branch_reloc_hash_match): Add hash3 and hash4.
      	(ppc64_elf_tls_optimize): Handle tga_desc_fd and tga_desc too.
      	(ppc64_elf_size_dynamic_sections): Likewise.
      	(ppc64_elf_relocate_section): Likewise.
      	(plt_stub_size, build_plt_stub): Likewise.  Size regsave
      	__tls_get_addr stub.
      	(build_tls_get_addr_stub): Build regsave __tls_get_addr stub and
      	eh_frame.
      	(ppc_size_one_stub): Handle tga_desc_fd and tga_desc too.  Size
      	eh_frame for regsave __tls_get_addr.
      gas/
      	* config/tc-ppc.c (parse_tls_arg): Handle tls arg for
      	__tls_get_addr_desc and __tls_get_addr_opt.
      ld/
      	* emultempl/ppc64elf.em (ppc64_opt, PARSE_AND_LIST_LONGOPTS),
      	(PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Support
      	--tls-get-addr-regsave and --no-tls-get-addr-regsave.
      	(params): Init new field.
      	* ld.texi (--tls-get-addr-regsave, --no-tls-get-addr-regsave):
      	Document.
      	* testsuite/ld-powerpc/tlsdesc.s,
      	* testsuite/ld-powerpc/tlsdesc.d,
      	* testsuite/ld-powerpc/tlsdesc.wf,
      	* testsuite/ld-powerpc/tlsdesc2.d,
      	* testsuite/ld-powerpc/tlsdesc2.wf,
      	* testsuite/ld-powerpc/tlsexenors.d,
      	* testsuite/ld-powerpc/tlsexenors.r,
      	* testsuite/ld-powerpc/tlsexers.d,
      	* testsuite/ld-powerpc/tlsexers.r,
      	* testsuite/ld-powerpc/tlsexetocnors.d,
      	* testsuite/ld-powerpc/tlsexetocrs.d,
      	* testsuite/ld-powerpc/tlsexetocrs.r,
      	* testsuite/ld-powerpc/tlsopt6.d,
      	* testsuite/ld-powerpc/tlsopt6.wf: New.
      	* testsuite/ld-powerpc/powerpc.exp: Run new tests.
      9e7028aa
    • Alan Modra's avatar
      PowerPC64 TLS optimization fix · abc489c6
      Alan Modra authored
      When linking with --no-tls-optimize the linker doesn't generate a call
      or long branch stub to __tls_get_addr in some circumstances, giving:
      
      relocation truncated to fit: R_PPC64_REL24 against symbol `__tls_get_addr'
      
      	* elf64-ppc.c (ppc64_elf_size_stubs): Correct condition under
      	which __tls_get_addr calls will be eliminated.
      abc489c6
    • Yuri Chornoivan's avatar
      PR25417, Fix minor typos · c48acf6f
      Yuri Chornoivan authored
      	PR 25417
      binutils/
      	* readelf.c (get_alpha_symbol_other): Fix error message typo.
      ld/
      	* ldlang.c (ldlang_open_ctf): Fix error message typo.
      	* emultempl/z80elf.em (z80_elf_after_open): Likewise.
      c48acf6f
    • H.J. Lu's avatar
      pr23900-1.d: Adjusted · 1e161364
      H.J. Lu authored
      Linux program headers may look like
      
      Section to Segment mapping:
        Segment Sections...
         00     .note.gnu.property .text
         01     .note.gnu.property
         02     .note.gnu.property
      
      or
      
      Section to Segment mapping:
        Segment Sections...
         00     .note.gnu.property
         01     .text
         02     .note.gnu.property
         03     .note.gnu.property
      
      Update pr23900-1.d to accept both.
      
      	* testsuite/ld-elf/pr23900-1.d: Adjusted.
      1e161364
    • GDB Administrator's avatar
      Automatic date update in version.in · ea91954d
      GDB Administrator authored
      ea91954d
  4. 21 Jan, 2020 13 commits
    • Simon Marchi's avatar
      gdb: add declaration for _initialize_gdbarch in gdbarch.sh · a1237872
      Simon Marchi authored
      In commit
      
        gdb: add back declarations for _initialize functions
        6c265988
      
      I wrongfully edited gdbarch.c, instead of editing gdbarch.sh and
      re-generating gdbarch.c.  This patch fixes gdbarch.sh to add a
      declaration for _initialize_gdbarch.  gdbarch.c is not changed, as the
      output of gdbarch.sh now matches the current state of gdbarch.c.
      
      gdb/ChangeLog:
      
      	* gdbarch.sh: Add declaration for _initialize_gdbarch.
      a1237872
    • Simon Marchi's avatar
      gdb: remove uses of iterate_over_inferiors in remote-sim.c · b3ee6dd9
      Simon Marchi authored
      This removes the two uses of iterate_over_inferiors, in favor of
      range-based loops.
      
      gdb/ChangeLog:
      
      	* remote-sim.c (check_for_duplicate_sim_descriptor): Remove.
      	(get_sim_inferior_data): Remove use of iterate_over_inferiors,
      	replace with range-based for.
      	(gdbsim_interrupt_inferior): Remove.
      	(gdbsim_target::interrupt): Replace iterate_over_inferiors use
      	with a range-based for.  Inline code from
      	gdbsim_interrupt_inferior.
      b3ee6dd9
    • Simon Marchi's avatar
      gdb: fix indentation in infrun.c · f9fac3c8
      Simon Marchi authored
      I noticed the indentation there was off, this patch fixes it.
      
      gdb/ChangeLog:
      
      	* infrun.c (proceed): Fix indentation.
      f9fac3c8
    • Tom Tromey's avatar
      Allow use of Pygments to colorize source code · f6474de9
      Tom Tromey authored
      While GNU Source Highlight is good, it's also difficult to build and
      distribute.  For one thing, it needs Boost.  For another, it has an
      unusual configuration and installation setup.
      
      Pygments, a Python library, doesn't suffer from these issues, and so I
      thought it would be a reasonable fallback.
      
      This patch implements this idea.  GNU Source Highlight is preferred,
      but if it is unavailable (or fails), the extension languages are
      tried.  This patch also implements support for Pygments.
      
      Something similar could be done for Guile, using:
      
          https://dthompson.us/projects/guile-syntax-highlight.html
      
      However, I don't know enough about Guile internals to make this
      happen, so I have not done it here.
      
      gdb/ChangeLog
      2020-01-21  Tom Tromey  <tromey@adacore.com>
      
      	* source-cache.c (source_cache::ensure): Call ext_lang_colorize.
      	* python/python.c (python_extension_ops): Update.
      	(gdbpy_colorize): New function.
      	* python/lib/gdb/__init__.py (colorize): New function.
      	* extension.h (ext_lang_colorize): Declare.
      	* extension.c (ext_lang_colorize): New function.
      	* extension-priv.h (struct extension_language_ops) <colorize>: New
      	member.
      	* cli/cli-style.c (_initialize_cli_style): Update help text.
      
      Change-Id: I5e21623ee05f1f66baaa6deaeca78b578c031bf4
      f6474de9
    • H.J. Lu's avatar
      pr23900-1.d: Also check PT_GNU_PROPERTY program header · b4654b10
      H.J. Lu authored
      Also pass -l to readelf to check PT_GNU_PROPERTY program header.
      
      	PR ld/23900
      	* testsuite/ld-elf/pr23900-1.d: Also pass -l to readelf.
      b4654b10
    • Jan Beulich's avatar
      x86: testsuite adjustments after commit 1a035124 · e3ed17f3
      Jan Beulich authored
      The odd behavior of certain COFF/PE targets makes necessary some
      mechanical adjustments.
      e3ed17f3
    • Luis Machado's avatar
      Convert an int flag variable to bool · f0c702d4
      Luis Machado authored
      As suggested, the cond variable is really supposed to be a bool. So,
      make it so.
      
      gdb/ChangeLog:
      
      2020-01-21  Luis Machado  <luis.machado@linaro.org>
      
      	* aarch64-tdep.c (struct aarch64_displaced_step_closure)
      	<cond>: Change type to bool.
      	(aarch64_displaced_step_b_cond): Update cond to use bool type.
      	(aarch64_displaced_step_cb): Likewise.
      	(aarch64_displaced_step_tb): Likewise.
      f0c702d4
    • Luis Machado's avatar
      Add more debugging output to aarch64_displaced_step_fixup · 1ab139e5
      Luis Machado authored
      While debugging the step-over-syscall problem, i wanted to see a bit more
      debugging output to try to determine the root cause.
      
      This patch does this.
      
      gdb/ChangeLog:
      
      2020-01-21  Luis Machado  <luis.machado@linaro.org>
      
      	* aarch64-tdep.c (aarch64_displaced_step_fixup): Add more debugging
      	output.
      1ab139e5
    • Luis Machado's avatar
      Fix step-over-syscall.exp failure · 0c271889
      Luis Machado authored
      In particular, this one:
      
      FAIL: gdb.base/step-over-syscall.exp: fork: displaced=on: check_pc_after_cross_syscall: single step over fork final pc
      
      When ptrace fork event reporting is enabled, GDB gets a PTRACE_EVENT_FORK
      event whenever the inferior executes the fork syscall.
      
      Then the logic is that GDB needs to step the inferior yet again in order to
      receive a predetermined SIGTRAP, but no execution takes place because the
      signal was already queued for delivery. That means the PC should stay the same.
      
      I noticed the aarch64 code is currently adjusting the PC in this situation,
      making the inferior skip an instruction without executing it.
      
      The following change checks if we did not execute the instruction
      (pc - to == 0), making proper adjustments for such case.
      
      Regression tested on aarch64-linux-gnu on the tryserver.
      
      gdb/ChangeLog:
      
      2020-01-21  Luis Machado  <luis.machado@linaro.org>
      
      	* aarch64-tdep.c (struct aarch64_displaced_step_closure )
      	<pc_adjust>: Adjust the documentation.
      	(aarch64_displaced_step_fixup): Check if PC really moved before
      	adjusting it.
      0c271889
    • Jan Beulich's avatar
      x86: replace adhoc ambiguous operand checking for CRC32 · 1a035124
      Jan Beulich authored
      There's no need (anymore?) to heavily special case this - just make
      generic logic consider only its first operand, and deal with the case
      of an 'l' suffix not being allowed in a pattern.
      1a035124
    • Jan Beulich's avatar
      x86: improve handling of insns with ambiguous operand sizes · c006a730
      Jan Beulich authored
      Commit b76bc5d5 ("x86: don't default variable shift count insns to
      8-bit operand size") pointed out a very bad case, but the underlying
      problem is, as mentioned on various occasions, much larger: Silently
      selecting a (nowhere documented afaict) certain default operand size
      when there's no "sizing" suffix and no suitable register operand(s) is
      simply dangerous (for the programmer to make mistakes).
      
      While in Intel syntax mode such mistakes already lead to an error (which
      is going to remain that way), AT&T syntax mode now gains warnings in
      such cases by default, which can be suppressed or promoted to an error
      if so desired by the programmer. Furthermore at least general purpose
      insns now consistently have a default applied (alongside the warning
      emission), rather than accepting some and refusing others.
      
      No warnings are (as before) to be generated for "DefaultSize" insns as
      well as ones acting on selector and other fixed-width values. For
      SYSRET, however, the DefaultSize needs to be dropped - it had been
      wrongly put there in the first place, as it's unrelated to .code16gcc
      (no stack accesses involved).
      
      As set forth as a prereq when I first mentioned this intended change a
      few years back, Linux as well as gcc have meanwhile been patched to
      avoid (emission of) ambiguous operands (and hence triggering of the new
      warning).
      
      Note that I think that in 64-bit mode IRET and far RET would better get
      a diagnostic too, as it's reasonably likely that a suffix-less instance
      really is meant to be a 64-bit one. But I guess I better make this a
      separate follow-on patch.
      
      Note further that floating point operations with integer operands are an
      exception for now: They continue to use short (16-bit) operands by
      default even in 32- and 64-bit modes.
      
      Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
      need to be diagnosed, with their 64-bit forms not being very useful I
      think it is better to continue to avoid warning about them (by way of
      them carrying IgnoreSize attributes).
      c006a730
    • Jan Beulich's avatar
      x86: VCVTNEPS2BF16{X,Y} should permit broadcasting · c906a69a
      Jan Beulich authored
      Just like other VCVT*{X,Y} templates do, and to allow the programmer
      flexibility (might be relevant in particular when heavily macro-izing
      code), the two templates should also have Broadcast set, just like their
      X/Y-suffix-less counterparts. This in turn requires them to also have
      * Dword set on their memory operands, to cover the logic added to
        i386gen by 4a1b91ea ("x86: Expand Broadcast to 3 bits"),
      * RegXMM/RegYMM set on their source operands, to satisfy broadcast
        sizing logic in gas itself.
      Otherwise ATTSyntax templates wouldn't need such operand size attributes.
      
      While extending the test cases, also add Intel syntax broadcast forms
      without explicit size specifiers.
      c906a69a
    • GDB Administrator's avatar
      Automatic date update in version.in · 53570fbc
      GDB Administrator authored
      53570fbc
  5. 20 Jan, 2020 7 commits
    • Nick Clifton's avatar
      26916852
    • H.J. Lu's avatar
      x86-64: Fix TLSDESC relaxation for x32 · 14470f07
      H.J. Lu authored
      For x32, we must encode "lea x@TLSDESC(%rip), %reg" with a REX prefix
      even if it isn't required.  Otherwise linker can’t safely perform
      GDesc -> IE/LE optimization.  X32 TLSDESC sequences can be:
      
      40 8d 05 00 00 00 00	rex lea	x@TLSDESC(%rip), %reg
      ...
      67 ff 10		call	*x@TLSCALL(%eax)
      
      or the same sequence as LP64:
      
      48 8d 05 00 00 00 00	lea	foo@TLSDESC(%rip), %reg
      ...
      ff 10			call	*foo@TLSCALL(%rax)
      
      We need to support both sequences for x32.  For both GDesc -> IE/LE
      transitions,
      
      67 ff 10		call	*x@TLSCALL(%eax)
      
      should relaxed to
      
      0f 1f 00		nopl	(%rax)
      
      For GDesc -> LE transition,
      
      40 8d 05 00 00 00 00	rex lea	x@TLSDESC(%rip), %reg
      
      should relaxed to
      
      40 c7 c0 fc ff ff ff	rex movl $x@tpoff, %reg
      
      For GDesc -> IE transition,
      
      40 8d 05 00 00 00 00	rex lea	x@TLSDESC(%rip), %reg
      
      should relaxed to
      
      40 8b 05 00 00 00 00	rex movl x@gottpoff(%rip), %eax
      
      bfd/
      
      	PR ld/25416
      	* elf64-x86-64.c (elf_x86_64_check_tls_transition): Support
      	"rex leal x@tlsdesc(%rip), %reg" and "call *x@tlsdesc(%eax)" in
      	X32 mode.
      	(elf_x86_64_relocate_section): In x32 mode, for GDesc -> LE
      	transition, relax "rex leal x@tlsdesc(%rip), %reg" to
      	"rex movl $x@tpoff, %reg", for GDesc -> IE transition, relax
      	"rex leal x@tlsdesc(%rip), %reg" to
      	"rex movl x@gottpoff(%rip), %eax".  For both transitions, relax
      	"call *(%eax)" to "nopl (%rax)".
      
      gas/
      
      	PR ld/25416
      	* config/tc-i386.c (output_insn): Add a dummy REX_OPCODE prefix
      	for lea with R_X86_64_GOTPC32_TLSDESC relocation when generating
      	x32 object.
      	* testsuite/gas/i386/ilp32/x32-tls.d: Updated.
      	* testsuite/gas/i386/ilp32/x32-tls.s: Add tests for lea with
      	R_X86_64_GOTPC32_TLSDESC relocation.
      
      ld/
      
      	PR ld/25416
      	* testsuite/ld-x86-64/pr25416-1.s: New file
      	* testsuite/ld-x86-64/pr25416-1a.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-1b.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-1.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-2.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-2a.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-2b.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-3.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-3.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-4.d: Likewise.
      	* testsuite/ld-x86-64/pr25416-4.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-5a.c: Likewise.
      	* testsuite/ld-x86-64/pr25416-5b.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-5c.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-5d.s: Likewise.
      	* testsuite/ld-x86-64/pr25416-5e.s: Likewise.
      	* testsuite/ld-x86-64/x86-64.exp: Run PR ld/25416 tests.
      14470f07
    • Alan Modra's avatar
      Don't touch r11 in __tls_get_addr stub · b9ca1af6
      Alan Modra authored
      This modifies the special __tls_get_addr stub that checks for a
      tlsdesc style __tls_index entry and returns early.  Not using r11
      isn't much benefit at the moment but a followup patch will preserve
      regs around the first call to __tls_get_addr when the __tls_index
      entry isn't yet set up for an early return.
      
      bfd/
      	* elf64-ppc.c (LD_R11_0R3, CMPDI_R11_0, STD_R11_0R1, LD_R11_0R1),
      	(MTLR_R11): Don't define.
      	(LD_R0_0R3, CMPDI_R0_0): Define.
      	(build_tls_get_addr_stub): Don't use r11 in stub.
      ld/
      	* testsuite/ld-powerpc/tlsexe.d: Match new __tls_get_addr stub.
      	* testsuite/ld-powerpc/tlsexeno.d: Likewise.
      	* testsuite/ld-powerpc/tlsexetoc.d: Likewise.
      	* testsuite/ld-powerpc/tlsexetocno.d: Likewise.
      	* testsuite/ld-powerpc/tlsopt5.d: Likewise.
      b9ca1af6
    • Alan Modra's avatar
      PowerPC64 ppc_elf_hash_entry, defined_sym_val, is_tls_get_addr · ed7007c1
      Alan Modra authored
      	* elf64-ppc.c (ppc_elf_hash_entry): New function, use throughout file.
      	(defined_sym_val, is_tls_get_addr): Likewise.
      ed7007c1
    • Alan Modra's avatar
      ubsan: hppa: negation of -2147483648 · 4d6cbb64
      Alan Modra authored
      	* hppa-dis.c (fput_const): Remove useless cast.
      4d6cbb64
    • Alan Modra's avatar
      ubsan: arm: out of bounds array access · 2bddb71a
      Alan Modra authored
       .inst 0x81bdfe9f
      
      disassembles as
         0:	81bdfe9f 	ldaexdhi	pc, reg-names-std, [sp]
      
      I'm quite sure "reg-names-std" isn't an ARM register.
      
      	* arm-dis.c (print_insn_arm): Wrap 'T' value.
      2bddb71a
    • Simon Marchi's avatar
      sim: don't rely on inferior_ptid in gdbsim_target::wait · cf1d9e09
      Simon Marchi authored
      When running a program with the simulator target, I get:
      
          /home/simark/src/binutils-gdb/gdb/inferior.c:279: internal-error: inferior* find_inferior_pid(process_stratum_target*, int): Assertion `pid != 0' failed.
      
      This can be reproduced by building a GDB for --target=arm-none-gnueabi,
      and running with
      
          $ ./gdb -nx --data-directory=data-directory a.out -ex "target sim" -ex load -ex "b main" -ex r
      
      Where a.out is any program with a main.
      
      The problem is that gdbsim_target::wait assumes that inferior_ptid has
      the value of the thread it wants to report an event for.
      
      Actually, it's the target's responsibility to come up with the ptid of
      the thread the event is for.  In the sim target, that ptid is stored in
      sim_inferior_data::remote_sim_ptid, so return that instead of
      inferior_ptid.
      
      ChangeLog:
      
      	* remote-sim.c (gdbsim_target::wait): Return
      	sim_data->remote_sim_ptid instead of inferior_ptid.
      cf1d9e09