- 19 Jul, 2019 2 commits
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Flora Cui authored
1. perform gpu reset 2. perform dispatch test to verify gpu reset to a good state Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com>
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Flora Cui authored
1. skip test if there's no desired ring 2. clear shader buffer 3. update command buffer for gfx9 Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com>
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- 03 Jul, 2019 6 commits
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Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric.engestrom@intel.com>
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Eric Engestrom authored
Signed-off-by:
Eric Engestrom <eric.engestrom@intel.com>
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Eric Engestrom authored
Adapted from a local patch carried by DragonFlyBSD: https://github.com/DragonFlyBSD/DPorts/blob/bc056f88f7e4d468d8c9751f831a47b5ae1326e3/graphics/libdrm/files/patch-xf86drm.h Patch is sadly uncredited (a bot authored the commit), so I can't credit the author here either. Signed-off-by:
Eric Engestrom <eric.engestrom@intel.com>
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Jonathan Gray authored
drm render nodes have the same major as drm primary devices but offset the minor by a base of 128. I expected the name of the device to have numbering starting at 0 when these non-linux codepaths were added (before OpenBSD had render nodes). Signed-off-by:
Jonathan Gray <jsg@jsg.id.au> Acked-by:
Eric Engestrom <eric.engestrom@intel.com>
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Jonathan Gray authored
Unlike Linux the OpenBSD primary "drm" device name is substring of the "drmR" render node device name and strncmp() tests resulted in render nodes being flagged as primary nodes. Signed-off-by:
Jonathan Gray <jsg@jsg.id.au> Reviewed-by:
Eric Engestrom <eric.engestrom@intel.com> Acked-by:
Eric Engestrom <eric.engestrom@intel.com>
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Ilia Mirkin authored
Make it actually clear the LUT. Reported-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Dave Airlie <airlied@redhat.com>
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- 02 Jul, 2019 1 commit
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Marek Olšák authored
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- 01 Jul, 2019 3 commits
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Michel Dänzer authored
Seems to better reflect what they're for. Reviewed-by:
Emil Velikov <emil.l.velikov@gmail.com>
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Michel Dänzer authored
Simplifies its callers. dev->bo_table_mutex is now always held when amdgpu_bo_create is called (this was already the case in amdgpu_bo_import). Reviewed-by:
Emil Velikov <emil.l.velikov@gmail.com>
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Michel Dänzer authored
And propagate drmIoctl's return value. This allows replacing all remaining open-coded DRM_IOCTL_GEM_CLOSE ioctl calls with amdgpu_close_kms_handle calls. Reviewed-by:
Emil Velikov <emil.l.velikov@gmail.com>
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- 28 Jun, 2019 1 commit
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Marek Vasut authored
The following situation can happen in a multithreaded OpenGL application. A BO is submitted from etna_cmd_stream #1 with flags set for read. A BO is submitted from etna_cmd_stream #2 with flags set for write. This triggers a flush on stream #1 and clears the BO's current_stream pointer. If at this point, stream #2 attempts to queue BO again, which does happen, the BO will be added to the submit list twice. The Linux kernel driver correctly detects this and warns about it with "BO at index %u already on submit list" kernel message. However, when cleaning the BO cache in etna_bo_cache_free(), the BO which was submitted twice will also be free()d twice, this triggering a glibc double free detector. The fix is easy, even if the BO does not have current_stream set, iterate over current streams' list of BOs before adding the BO to it and verify that the BO is not yet there. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by:
Wladimir J. van der Laan <laanwj@gmail.com>
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- 25 Jun, 2019 2 commits
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Michel Dänzer authored
To reflect current reality. Reviewed-by:
Christian König <christian.koenig@amd.com>
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Michel Dänzer authored
Avoids compiler warning: ../../amdgpu/amdgpu_cs.c: In function 'amdgpu_cs_ctx_override_priority': ../../amdgpu/amdgpu_cs.c:155:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] union drm_amdgpu_sched args; ^~~~~ Reviewed-by:
Christian König <christian.koenig@amd.com>
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- 24 Jun, 2019 1 commit
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Lucas Stach authored
There is no implementation and also no users, so there is no point in keeping it in the API. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de>
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- 22 Jun, 2019 11 commits
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Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
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Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
Instead of hacking the binary every time, we can now specify directly. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
This includes logic to configure the LUT accordingly. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
As new features are added and others are declared to be legacy, it's nice to be able to implement fallbacks. As such, create a property-setting variant that does not generate errors which can very well be entirely expected. Will be used for gamma control in a future change. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
This change adds support for all current patterns. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
The idea is to have a horizontal pattern split into two with the top and bottom halves having different precision. This allows one to see whether 10bpc support is working properly or not, as there are many pieces to the puzzle beyond the basic format support (gamma ramps, bpc encodings, etc). This is really only useful on 10bpc formats, but we also add support for 8bpc formats to ease testing. In the future, this could be applied to 16bpc formats as well. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
We need to shift the values up, otherwise we'd end up with a negative shift. This works for up-to 16-bit components, which is fine for now. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
Emil Velikov <emil.velikov@collabora.com>
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Ilia Mirkin authored
This also adds a helper to generate a color LUT, which has to be used in conjunction with the C8 indexed format. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Acked-by:
Emil Velikov <emil.velikov@collabora.com>
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- 21 Jun, 2019 4 commits
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Leo Liu authored
With different register offsets from VCN1.0 Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
Marek Olšák <marek.olsak@amd.com>
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Tao Zhou authored
AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10 Reviewed-by:
Tim Writer <Tim.Writer@amd.com> Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Marek Olšák <marek.olsak@amd.com>
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Hawking Zhang authored
pa_sc_tile_steering_override is a new member introduced for gfx10 Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Marek Olšák <marek.olsak@amd.com>
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Huang Rui authored
Reviewed-by:
Tim Writer <Tim.Writer@amd.com> Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Marek Olšák <marek.olsak@amd.com>
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- 11 Jun, 2019 2 commits
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Chunming Zhou authored
Feature is controlled by DRM_CAP_SYNCOBJ_TIMELINE drm capability. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com>
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Chunming Zhou authored
a) delta: only DRM_CAP_SYNCOBJ_TIMELINE b) Generated using make headers_install. c) Generated from origin/drm-misc-next commit 982c0500fd1a8012c31d3c9dd8de285129904656" Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Suggested-by:
Michel Dänzer <michel@daenzer.net> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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- 16 May, 2019 7 commits
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Michel Dänzer authored
Fixes make check. Trivial.
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Chunming Zhou authored
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation, fix some warnings v3: add export/import and cpu signal testing cases Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Chunming Zhou authored
v2: adapt to new one transfer ioctl Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Chunming Zhou authored
v2: use one transfer ioctl Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Chunming Zhou authored
v2: symbos are stored in lexical order. v3: drop export/import and extra query indirection Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Chunming Zhou authored
v2: drop export/import Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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