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- Jun 04, 2021
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Benjamin Gaignard authored
Forward ported from 4.19 Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
DSI device use the information from the sensor to configure the number of used lanes. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
rk3566 EVB needs to drive power down gpio Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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- May 28, 2021
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Support YUV420 format inside DSI hardware block. Tell to display engine to produce YUV420 data. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Add an enum entry to define MIPI DSI YUV420 format Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Enable simple panel driver. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Change evb panel to simple panel dsi like done in vendor kernel. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Forward port the hooks done in simple panel for rk3568 evb display Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Add configurations flags to be able to use the display on EVB. Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by:
Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Signed-off-by:
XiaoDong Huang <derrick.huang@rock-chips.com>
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Signed-off-by:
Liang Chen <cl@rock-chips.com>
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Signed-off-by:
XiaoDong Huang <derrick.huang@rock-chips.com>
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Signed-off-by:
XiaoDong Huang <derrick.huang@rock-chips.com>
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- May 20, 2021
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Ezequiel Garcia authored
During the submission of the clk-rk3568 driver, some bugs were fixed, so the mainline driver is slightly different than ours. Backport those changes. Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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Before the change: The sizeof rk3568_pll_rates = 2544 Use union: The sizeof rk3568_pll_rates = 1696 In future Soc, more PLL types will be added, and the rockchip_pll_rate_table will add more members, and the space savings will be even more pronounced by using union. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com> Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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The cpll clk gate bits had an ordering issue. This led to the loss of the boot sdmmc controller when the gmac was shut down with: `ip link set eth0 down` as the cpll_100m was shut off instead of the cpll_62p5. cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m misplaced. Fixes: cf911d89 ("clk: rockchip: add clock controller for rk3568") Signed-off-by:
Peter Geis <pgwipeout@gmail.com>
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Ezequiel Garcia authored
The compatible string changed when it was merged upstream. Also get rid of the properties that were wrong or not needed. Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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sdhci based synopsys MMC IP is also used on some rockchip platforms, so add a basic support here. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com>
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This patch adds rockchip support in sdhci-of-dwcmhsc.yaml Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com>
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This patch converts sdhci-of-dwcmshc.txt to sdhci-of-dwcmshc.yaml Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by:
Rob Herring <robh@kernel.org>
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Ezequiel Garcia authored
Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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Add constants and callback functions for the dwmac present on RK3566/RK3568 SoCs. RK3568 has two MACs, and RK3566 just one, but it's otherwise the same IP core. Signed-off-by:
David Wu <david.wu@rock-chips.com> [Ezequiel: Separate rk3566-gmac support] Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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Ezequiel Garcia authored
This reverts commit e544eba0.
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Ezequiel Garcia authored
Rockchip's v4.19 kernel is removing this operating point on some of the boards. Looking at the datasheet, it's also unclear if the SoC can tolerate this voltage. Let's remove it. Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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Ezequiel Garcia authored
Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com>
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The tcs4525 is based off the fan53526. Rename the tcs4525 functions to align with this. Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210511211335.2935163-4-pgwipeout@gmail.com Signed-off-by:
Mark Brown <broonie@kernel.org>
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The tcs4525 regulator has a chip id of <12>. Only allow the driver to bind to the correct chip id for safety, in accordance with the other supported devices. Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210511211335.2935163-3-pgwipeout@gmail.com Signed-off-by:
Mark Brown <broonie@kernel.org>
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The TCS4525 has 128 voltage steps. With the calculation set to 127 the most significant bit is disregarded which leads to a miscalculation of the voltage by about 200mv. Fix the calculation to end deadlock on the rk3566-quartz64 which uses this as the cpu regulator. Fixes: 914df8fa ("regulator: fan53555: Add TCS4525 DCDC support") Signed-off-by:
Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20210511211335.2935163-2-pgwipeout@gmail.com Signed-off-by:
Mark Brown <broonie@kernel.org>
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We allocate 2MB chunks at a time, so it might appear that a page fault has already been handled by a previous page fault when we reach panfrost_mmu_map_fault_addr(). Bail out in that case to avoid mapping the same area twice. Cc: <stable@vger.kernel.org> Fixes: 187d2929 ("drm/panfrost: Add support for GPU heap allocations") Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Steven Price <steven.price@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210205111757.585248-3-boris.brezillon@collabora.com
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