- May 25, 2022
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Benjamin Gaignard authored
Luma and chroma depth are set on different hardware registers. Even if they aren't identical the bitstream can be compliant to HEVC specifications and decoded by the hardware. With this patch TSUNEQBD_A_MAIN10_Technicolor_2 conformance test is successfully decoded. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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- May 24, 2022
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Benjamin Gaignard authored
Documentation said that g2 init_qp field use bits 24 to 30 of the 8th register. Change the field mask to be able to set 7 bits and not only 6 of them. Conformance test INITQP_B_Main10_Sony_1 decoding is OK with this patch. Fixes: cb5dd5a0 ("media: hantro: Introduce G2/HEVC decoder") Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Move output format in postproc and make sure that 10bit configuration is correctly set. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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- May 23, 2022
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Benjamin Gaignard authored
Store HEVC bit depth in context. Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
SAO and FILTER buffers size depend of the bit depth. Make sure we have enough space for 10bit bitstreams. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Now that we have proper infrastructure for postprocessing 10-bit formats, store VP9 bit depth in context. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Benjamin Gaignard authored
Some postproc legacy registers were set in VP9 code. Move them to postproc and fix their value. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
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When allocating aux buffers for postprocessing, it's assumed that base buffer size is the same as that of output. Coincidentally, that's true most of the time, but not always. 10-bit source also needs aux buffer size which is appropriate for 10-bit native format, even if the output format is 8-bit. Similarly, mv sizes and other extra buffer size also depends on source width/height, not destination. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
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In preparation for supporting 10-bit formats, add mechanism which will filter formats based on pixel depth. Hantro G2 supports only one decoding format natively and that is based on bit depth of current video frame. Additionally, it makes no sense to upconvert bitness, so filter those out too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Add P010 tiled format Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> [rebased and updated pixel format name] Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Benjamin Gaignard authored
On Hantro G2 decoder on IMX8MQ strides requirements aren't the same for NV12_4L4 and NV12 pixel formats. The first one use a 4 bytes padding while the last one needs 8 bytes. To be sure to provide the correct stride in all cases we need: - to relax the constraints on codec formats so set step_width to 4 - use capture queue format and not the output queue format when applying the pixel format constraints. - put the correct step_width constraints on each pixel format. Move HEVC SPS validation in hantro_hevc.c to be able to perform it when setting sps control and when starting to decode the bitstream. Add a new test in HEVC SPS validation function to check if resolution is still matching the hardware constraints. With this SAODBLK_A_MainConcept_4 and SAODBLK_B_MainConcept_4 conformance tests files are correctly decoded with both NV12 and NV12_4L4 pixel formats. These two files have a resolution of 1016x760. If, for the both pixel formats, step_width equal 16 than the selected capture resolution is 1024x768 which is wrong for NV12_4L4 (which expect 1016x760) on Hantro G2 on IMX8MQ. Add defines for various resolutions. For other variants than Hantro G2 on IMX8M keep the same step_width to avoid regressions. Fluster HEVC test score is now 128/147 vs 126/147 with the both pixel formats as decoder output. Fluster VP9 test score stay at 147/303. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
PoC shall be int the range of -2^31 to 2^31 -1 (HEVC spec section 8.3.1 Decoding process for picture order count). The current way to know if an entry in reference picture array is free is to test if PoC = UNUSED_REF. Since UNUSED_REF is defined as '-1' that could lead to decode issue if one PoC also equal '-1'. PoC with value = '-1' exists in conformance test SLIST_B_Sony_9. Change the way unused entries are managed in reference pictures array to avoid using PoC to detect then. This patch doesn't change fluster HEVC score. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
HEVC uAPI is used by 2 mainline drivers (Hantro, Cedrus) and at least 2 out-of-tree drivers (rkvdec, RPi). The uAPI has been reviewed so it is time to make it 'public' by un-staging it. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
'F.7.3.6.1 General slice segment header syntax' section of HEVC specification describes that a slice header always end aligned on byte boundary, therefore we only need to provide the data offset in bytes. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Fix padding where needed to remove holes and stay align on cache boundaries Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
The number of bits to skip in the slice header can be computed in the driver by using sps, pps and decode_params information. This allow to remove Hantro dedicated control. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Simply print the type of the control. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Move the HEVC stateless controls types out of staging, and re-number them. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
The number of 'entry point offset' can be very variable. Instead of using a large static array define a v4l2 dynamic array of U32 (V4L2_CTRL_TYPE_U32). The number of entry point offsets is reported by the elems field and in struct v4l2_ctrl_hevc_slice_params.num_entry_point_offsets field. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Move HEVC pixel format since we are ready to stabilize the uAPI Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Make explicit that V4L2_CID_STATELESS_HEVC_SLICE_PARAMS control is a dynamic array control type. Some drivers may be able to receive multiple slices in one control to improve decoding performance. Define the max size of the dynamic that can driver can set in .dims = {}. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Add kernel-doc documentation for all the HEVC structures. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
The possible values for the field_pic field in the v4l2_hevc_dpb_entry structure are defined in the table D.2 in HEVC specification section D.3.3. Add flags and documentation for each of them. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
The HEVC specification describes the following: "PicOrderCntVal is derived as follows: PicOrderCntVal = PicOrderCntMsb + slice_pic_order_cnt_lsb The value of PicOrderCntVal shall be in the range of −2^31 to 2^31 − 1, inclusive." To match with these definitions change __u16 pic_order_cnt[2] into __s32 pic_order_cnt_val. Change v4l2_ctrl_hevc_slice_params->slice_pic_order_cnt to __s32 too. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
Change HEVC stateless controls names to V4L2_CID_STATELESS_HEVC instead of V4L2_CID_MPEG_VIDEO_HEVC be coherent with v4l2 naming convention. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
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Benjamin Gaignard authored
Complete the HEVC controls with missing fields from H.265 specifications. Even if these fields aren't used by the current mainlined drivers they will be required for (at least) the rkvdec driver. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Add a dynamic array test control to help test support for this feature. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Implement support for dynamically allocated arrays. Most of the changes concern keeping track of the number of elements of the array and the number of elements allocated for the array and reallocating memory if needed. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Add a new flag that indicates that this control is a dynamically sized array. Also document this flag. Currently dynamically sized arrays are limited to one dimensional arrays, but that might change in the future if there is a need for it. The initial use-case of dynamic arrays are stateless codecs. A frame can be divided in many slices, so you want to provide an array containing slice information for each slice. Typically the number of slices is small, but the standard allow for hundreds or thousands of slices. Dynamic arrays are a good solution since sizing the array for the worst case would waste substantial amounts of memory. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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Benjamin Gaignard authored
Hardware documentation said that G2 max frequency is 300MHz. Fix dts to be aligned with this value. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Benjamin Gaignard authored
P010 is a YUV format with 10-bits per component with interleaved UV. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
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- May 17, 2022
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Nicolas Dufresne authored
This is needed to optimize field decoding. Each field will be decoded into the same capture buffer. To be able to queue multiple buffers, we need to be able to ask the driver to hold the capture buffer. Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Nicolas Dufresne authored
This adds the required code to support field decoding. While most of the code is derived from Rockchip and VSI reference code, the reduction of the reference list to 16 entries was found by trial and errors. The list consists of all the references with the opposite field parity. The strategy is to deduplicate the reference picture that points to the same storage (same index). The choice of opposite parity has been made to keep the other field of the current field pair in the list. This method may not be robust if a field was lost. [hverkuil: fix typos in the comment before deduplicate_reflist()] [hverkuil: document new cur_poc field] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Jonas Karlman authored
The driver maintains stable slot locations for reference pictures. This change makes the code more robust by using the reference_ts as key and by marking all entries invalid right from the start. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Nicolas Dufresne authored
The hardware expects FrameNumWrap or long_term_frame_idx. Picture numbers are per field, and are mostly used during the memory management process, which is done in userland. This fixes two ITU conformance tests: - MR6_BT_B - MR8_BT_B Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Nicolas Dufresne authored
In order to support interlaced video decoding, the driver must allow holding the capture buffer so that the second field can be decoded into it. Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Nicolas Dufresne authored
This makes use of the new feature in the reference builder to program up to 32 references when doing field decoding. It also signals the parity (top or bottom) of the field to the hardware. Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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Jonas Karlman authored
Ensure decoded CAPTURE buffer resolution is larger or equal to the coded OUTPUT buffer resolution. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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