- Jun 15, 2022
-
-
Benjamin Gaignard authored
Luma and chroma depth are set on different hardware registers. Even if they aren't identical the bitstream can be compliant to HEVC specifications and decoded by the hardware. With this patch TSUNEQBD_A_MAIN10_Technicolor_2 conformance test is successfully decoded. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Move output format in postproc and make sure that 10bit configuration is correctly set. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Store HEVC bit depth in context. Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
SAO and FILTER buffers size depend of the bit depth. Make sure we have enough space for 10bit bitstreams. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Now that we have proper infrastructure for postprocessing 10-bit formats, store VP9 bit depth in context. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-
Benjamin Gaignard authored
Some postproc legacy registers were set in VP9 code. Move them to postproc and fix their value. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-
When allocating aux buffers for postprocessing, it's assumed that base buffer size is the same as that of output. Coincidentally, that's true most of the time, but not always. 10-bit source also needs aux buffer size which is appropriate for 10-bit native format, even if the output format is 8-bit. Similarly, mv sizes and other extra buffer size also depends on source width/height, not destination. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-
In preparation for supporting 10-bit formats, add mechanism which will filter formats based on pixel depth. Hantro G2 supports only one decoding format natively and that is based on bit depth of current video frame. Additionally, it makes no sense to upconvert bitness, so filter those out too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-
Add P010 tiled format Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> [rebased and updated pixel format name] Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-
Benjamin Gaignard authored
PoC shall be int the range of -2^31 to 2^31 -1 (HEVC spec section 8.3.1 Decoding process for picture order count). The current way to know if an entry in reference picture array is free is to test if PoC = UNUSED_REF. Since UNUSED_REF is defined as '-1' that could lead to decode issue if one PoC also equal '-1'. PoC with value = '-1' exists in conformance test SLIST_B_Sony_9. Change the way unused entries are managed in reference pictures array to avoid using PoC to detect then. This patch doesn't change fluster HEVC score. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
HEVC uAPI is used by 2 mainline drivers (Hantro, Cedrus) and at least 2 out-of-tree drivers (rkvdec, RPi). The uAPI has been reviewed so it is time to make it 'public' by un-staging it. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
'F.7.3.6.1 General slice segment header syntax' section of HEVC specification describes that a slice header always end aligned on byte boundary, therefore we only need to provide the data offset in bytes. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Fix padding where needed to remove holes and stay aligned on cache boundaries Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
The number of bits to skip in the slice header can be computed in the driver by using sps, pps and decode_params information. This makes it possible to remove Hantro dedicated control. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Simply print the type of the control. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Move the HEVC stateless controls types out of staging, and re-number them. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
The number of 'entry point offset' can be very variable. Instead of using a large static array define a v4l2 dynamic array of U32 (V4L2_CTRL_TYPE_U32). The number of entry point offsets is reported by the elems field and in struct v4l2_ctrl_hevc_slice_params.num_entry_point_offsets field. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Move HEVC pixel format since we are ready to stabilize the uAPI Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Make explicit that V4L2_CID_STATELESS_HEVC_SLICE_PARAMS control is a dynamic array control type. Some drivers may be able to receive multiple slices in one control to improve decoding performance. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Add kernel-doc documentation for all the HEVC structures. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
- Jun 14, 2022
-
-
Benjamin Gaignard authored
The possible values for the field_pic field in the v4l2_hevc_dpb_entry structure are defined in the table D.2 in HEVC specification section D.3.3. Add flags and documentation for each of them. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
The HEVC specification describes the following: "PicOrderCntVal is derived as follows: PicOrderCntVal = PicOrderCntMsb + slice_pic_order_cnt_lsb The value of PicOrderCntVal shall be in the range of −2^31 to 2^31 − 1, inclusive." To match with these definitions change __u16 pic_order_cnt[2] into __s32 pic_order_cnt_val. Change v4l2_ctrl_hevc_slice_params->slice_pic_order_cnt to __s32 too. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Benjamin Gaignard authored
Change HEVC stateless controls names to V4L2_CID_STATELESS_HEVC instead of V4L2_CID_MPEG_VIDEO_HEVC be coherent with v4l2 naming convention. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
-
Benjamin Gaignard authored
Complete the HEVC controls with missing fields from H.265 specifications. Even if these fields aren't used by the current mainlined drivers they will be required for (at least) the rkvdec driver. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
Add a dynamic array test control to help test support for this feature. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
-
Implement support for dynamically allocated arrays. Most of the changes concern keeping track of the number of elements of the array and the number of elements allocated for the array and reallocating memory if needed. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
-
Add a new flag that indicates that this control is a dynamically sized array. Also document this flag. Currently dynamically sized arrays are limited to one dimensional arrays, but that might change in the future if there is a need for it. The initial use-case of dynamic arrays are stateless codecs. A frame can be divided in many slices, so you want to provide an array containing slice information for each slice. Typically the number of slices is small, but the standard allow for hundreds or thousands of slices. Dynamic arrays are a good solution since sizing the array for the worst case would waste substantial amounts of memory. Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
-
Benjamin Gaignard authored
Hardware documentation said that G2 max frequency is 300MHz. Fix dts to be aligned with this value. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-
- Jun 10, 2022
-
-
Dongliang Mu authored
The error handling code in pvr2_hdw_create forgets to unregister the v4l2 device. When pvr2_hdw_create returns back to pvr2_context_create, it calls pvr2_context_destroy to destroy context, but mp->hdw is NULL, which leads to that pvr2_hdw_destroy directly returns. Fix this by adding v4l2_device_unregister to decrease the refcount of usb interface. Reported-by: <syzbot+77b432d57c4791183ed4@syzkaller.appspotmail.com> Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Niklas Söderlund authored
When converting to full Virtual Channel routing an error crept into the routing table for Ebisu (r8a77990). The routing information is used at probe time preventing rcar-vin from probing correctly on this SoC, solve by correcting the routing table. Fixes: 3e52419e ("media: rcar-{csi2,vin}: Move to full Virtual Channel routing per CSI-2 IP") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Justin Green authored
Set allow_cache_hints to 1 for the vb2_queue source and destination queues in the mediatek vcodec V4L2 driver. This allows us to allocate buffers with the V4L2_MEMORY_FLAG_NON_COHERENT set. On Mediatek SoCs, this enables caching for this memory, which vastly improves performance when being read from CPU. Read performance for these buffers is in turn important for detiling MM21 video frames in userspace software, such as libyuv or gstreamer. This change should be safe from race conditions since videobuf2 already invalidates or flushes the appropriate cache lines in its prepare() and finish() methods. Tested on a MT8183 SoC. Resulted in both correct detiling and a 10X speedup. Signed-off-by: Justin Green <greenjustin@chromium.org> Suggested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Ziyang Xuan authored
vfree(NULL) is safe. NULL check before vfree() is not needed. Delete them to simplify the code. Generated by coccinelle script: scripts/coccinelle/free/ifnullfree.cocci Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com> Reviewed-by: ming_qian <ming.qian@nxp.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Ming Qian authored
v4l2 m2m has supplied some helper function to handle drain, so the driver can use the helper function directly. Fixes: d8ebe298 ("media: imx-jpeg: Set V4L2_BUF_FLAG_LAST at eos") Signed-off-by: Ming Qian <ming.qian@nxp.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Ming Qian authored
The hardware can support any image size WxH, with arbitrary W (image width) and H (image height) dimensions. Align upwards buffer size for both encoder and decoder. and leave the picture resolution unchanged. For decoder, the risk of memory out of bounds can be avoided. For both encoder and decoder, the driver will lift the limitation of resolution alignment. For example, the decoder can support jpeg whose resolution is 227x149 the encoder can support nv12 1080P, won't change it to 1920x1072. Fixes: 2db16c6e ("media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder") Signed-off-by: Ming Qian <ming.qian@nxp.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Ming Qian authored
There is a hardware bug that it will load the first 128 bytes of configuration data twice, it will led to some configure error. so shift the configuration data 128 bytes, and make the first 128 bytes all zero, then hardware will load the 128 zero twice, and ignore them as garbage. then the configuration data can be loaded correctly Fixes: 2db16c6e ("media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder") Signed-off-by: Ming Qian <ming.qian@nxp.com> Reviewed-by: Mirela Rabulea <mirela.rabulea@nxp.com> Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Ming Qian authored
the register CAST_NOMFRSIZE_LO should be equal to CAST_STATUS16 the register CAST_NOMFRSIZE_HI should be equal to CAST_STATUS17 the register CAST_OFBSIZE_LO should be equal to CAST_STATUS18 the register CAST_OFBSIZE_HI should be equal to CAST_STATUS19 Fixes: 2db16c6e ("media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder") Signed-off-by: Ming Qian <ming.qian@nxp.com> Reviewed-by: Mirela Rabulea <mirela.rabulea@nxp.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Chengguang Xu authored
In error case of s5p_mfc_power_on() we should call clk_disable_unprepare() for the clocks(from pm->clocks[0] to pm->clocks[i-1]). Signed-off-by: Chengguang Xu <cgxu519@mykernel.net> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-
Kees Cook authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2][3]. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays [3] https://github.com/KSPP/linux/issues/78 Fixes: 9f599f35 ("media: amphion: add vpu core driver") Cc: Ming Qian <ming.qian@nxp.com> Cc: Shijie Qin <shijie.qin@nxp.com> Cc: Zhou Peng <eagle.zhou@nxp.com> Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Reviewed-by: ming_qian <ming.qian@nxp.com> Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
-