PANVK_COMPUTE_CORE_MASK and PANVK_FRAGMENT_CORE_MASK override the
corresponding driconf options if present.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>

These can be used to pin an application to specific cores. A tiler mask
option is not included because there is no current hardware that
includes more than one tiler.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>

This is needed for panvk, where we want to expose uint64 core masks. The
previous int parsing logic was technically UB rather than guaranteed
truncate-on-overflow, but was likely compiled to truncate in practice.
It is very unlikely that anyone was relying on this.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>

Erik Faye-Lund authored 1 month ago and Olivia Lee committed 1 month ago

This hooks up some driconfs for WSI, as well as the force_vk_vendor
DRIconf. Nothing panvk specific for now.

We only implement the destroy func to leverage the existing link, and we
only give vk_command_buffer the ops but not the pool.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

Use common tracking of cmd pool, cmd level and cmd state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

No longer need to track allocator, device or queue family.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

This way we avoid the confusing base.base or even base.base.base when
venus uses common objects. This also aligns with the naming of the other
drivers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34083>

Register spilling can cause us to require thread local storage (tls).
However, we were not adjusting the tls stack size space to account for
the tls needed for the extra xfb shader when transform feedback is
needed. We noticed this when testing register allocation in the
OpenGL CTS (for testing we had forced spilling where none happened
before).

Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33935>

Both GC7000 GPUs have the RA_WRITES_DEPTH feature, which needs a bit
more prodding to have valid fragcoord.zw components present in the
shader. This has been fixed by the previous commit, so we can remove
the related fails from the CI expectation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>

On GPUs with the RA_WRITE_DEPTH feature, passing Z and/or W values
to SH can be gated. It doesn't have any impact on performance, so
maybe it's just to be able to free those register slots for other,
currently unknown, values. For now simply enable passing both Z and
W to SH unconditionally to make those GPUs behave like the ones
without the RA_WRITE_DEPTH feature.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>

Update to rnndb commit 51dbdbd9b83a
("rnndb: document RA depth W forwarding gate").

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34081>

To get the right error code. Mostly shouldn't be winsys dependent
anyway, outside of the idea that if we explicitly emulate a device
we should just assume th euser knows what they're doing.

Fixes: c942d957 ("radv: fail to initialize when the AMD GPU generation is unsupported")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12792
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33964>

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12769


Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34078>

require_full_quads is incorrect because it isn't actually enabled by
quad operations. Use the newly-introduced needs_quad_helper_invocations
instead.

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Fixes: 264d8a67 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>

This is needed on Qualcomm, where there are separate fields to enable
just 3 fragments and all 4 fragments.

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Fixes: 264d8a67 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>

This currently treats coarse and fine derivatives the same, but Qualcomm
needs to know whether just coarse derivatives are used or fine
derivatives/quad ops are also used. Rename this to
needs_coarse_quad_helper_invocations make clear the difference from the
new field, needs_full_quad_helper_invocations.

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Fixes: 264d8a67 ("ir3: Set need_full_quad depending on info.fs.require_full_quads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>

Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33862>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

This isn't useful, and it was getting serialized resulting in garbage in
the blob and tests that check for consistent serialization failing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

The spec says this is allowed to be 0.

Cc: stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

This is now allowed in VK_KHR_maintenance8. Copies that reinterpret
D24S8 as any 32-bit format are also allowed, but they should already
work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

When we copy the depth aspect of a D32S8 image to or from a R32
image, we don't need to split the copy or modify the aspect mask. Limit
this path to "true" D32S8->D32S8 copies.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

We don't use the additional access flags for anything yet, but pass them
through to vk2tu_access in case we will need to for a future extension.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33780>

this just existed so upstream could build.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34075>

adds Apple modifiers from drm-misc-next:
https://cgit.freedesktop.org/drm-misc/commit/?id=c8619f5402cbcccfe58151b53421029852473e4c



Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34075>

We no longer need finalize_nir and thus we don't need to support
texcoord as well. This is a nice rs state cleanup.

This effectivelly reverts commits
0ac68019 and
d4b8e8a4. Also import the previous
location fixup from the state tracker, which was removed when the
unconditional nir_opt_varying pass was introduced.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33961>

This was added so we could report compile failures. Since we can
now just do that simply from create_vs/fs_state there is no need
for finalize_nir anymore.

Move the optimization loop to the beginning of create_vs/fs_state.
This could be probably optimized a bit more, but right now there
should be no functional change, we can improve the pass order later.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33961>

Fixes: 8328e575 ("ac/surface/gfx12: enable DCC 256B compressed blocks and reorder modifiers")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33702>

Reviewed-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34030>

Reviewed-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34030>

this was previously a no-op because the pointers were identical,
leading to an extra unref in check_framebuffer_surface_mutable()

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34077>

these fields are misleading and should always be replaced by either:
* the framebuffer width/height
* explicit function params to specify width/height

Co-authored-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33946>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34059>

This has the same format as CP_SQE_UCODE_DBG but for BV.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34059>

Handle the rearrangement of control registers, and dump a new section
with the rest of the control registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34059>