- Aug 01, 2024
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Detlev Casanova authored -
Detlev Casanova authored
Signed-off-by:
Detlev Casanova <detlev.casanova@collabora.com> -
Detlev Casanova authored
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Add constants and callback functions for the dwmac on RK3576 soc. Signed-off-by:
David Wu <david.wu@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
Some Rockchip devices put the phase settings into the dw_mmc controller. The feature is implemented in devices where the USRID register contains 0x20230002. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
v2 tuning will inherit pre-stage loader's phase settings for the first time, and do re-tune if necessary. Re-tune will still try the rough degrees, for instance, 90, 180, 270, 360 but continue to do the fine tuning if sample window isn't good enough. Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
This driver is modified to support RK3576 SoCs and lists the power domains. Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
Add support for the 5 rk3576 GPIO banks. This also adds support for optionnal support of the sys-grf syscon, used for i3c software controlled weak pull-up. Signed-off-by:
Steven Liu <steven.liu@rock-chips.com>
[rebase, reword commit message]
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
This adds the necessary data for handling otp on the rk3576. Signed-off-by:
Finley Xiao <finley.xiao@rock-chips.com>
[rebase, adapt clock names]
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
Add the clock tree definition for the new RK3576 SoC. Signed-off-by:
Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
[rebase and squash]
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
Detlev Casanova authored
Add board file for the rk3576 based ArmSoM Sige5 board. While the hardware offers plenty of peripherals and connectivity this basic implementation just handles things required to successfully boot Linux from SD card, connect via UART or Ethernet. Signed-off-by:Detlev Casanova <detlev.casanova@collabora.com> -
Detlev Casanova authored
This device tree contains all devices necessary for booting from network or SD Card. It supports CPU, CRU, PM domains, dma, interrupts, timers, UART and SDHCI (everything necessary to boot Linux on this system on chip) as well as Ethernet, I2C, SPI and OTP. Also add the necessary DT bindings for the SoC. Signed-off-by:
Liang Chen <cl@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase, squash and reword commit message]
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> -
Detlev Casanova authored
The ArmSoM Sige 5 board connects the rk806 PMIC on an i2c bus. Signed-off-by:Detlev Casanova <detlev.casanova@collabora.com>
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- Jul 30, 2024
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Enable HDMI input port of the RK3588 EVB1. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
The Rock 5B has a Micro HDMI port, which can be used for receiving HDMI data. This enables support for it. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com>
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- Jul 29, 2024
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The Rockchip RK3588 has a built-in HDMI receiver block from Synopsys. Let's enable the driver for it. Signed-off-by:Sebastian Reichel <sebastian.reichel@collabora.com> -
Add initial support for the Synopsys DesignWare HDMI RX Controller Driver used by Rockchip RK3588. The driver supports: - HDMI 1.4b and 2.0 modes (HDMI 4k@60Hz) - RGB888, YUV422, YUV444 and YCC420 pixel formats - CEC - EDID configuration The hardware also has Audio and HDCP capabilities, but these are not yet supported by the driver. Reviewed-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20240719124032.26852-5-shreeya.patel@collabora.com
Signed-off-by: Sebastian Reichel <sre@kernel.org> -
Add device tree support for Synopsys DesignWare HDMI RX Controller. Reviewed-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Link: https://lore.kernel.org/r/20240719124032.26852-4-shreeya.patel@collabora.com
Signed-off-by: Sebastian Reichel <sre@kernel.org> -
Document bindings for the Synopsys DesignWare HDMI RX Controller. Reviewed-by:
Rob Herring <robh@kernel.org>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240719124032.26852-3-shreeya.patel@collabora.com
Signed-off-by: Sebastian Reichel <sre@kernel.org> -
Add an entry for Synopsys DesignWare HDMI Receiver Controller Driver. Signed-off-by:
Shreeya Patel <shreeya.patel@collabora.com>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Link: https://lore.kernel.org/r/20240719124032.26852-2-shreeya.patel@collabora.com
Signed-off-by: Sebastian Reichel <sre@kernel.org> -
Enable Rockchip specific extensions for the Synopsys DesignWare HDMI QP driver. This is needed for the HDMI output support on RK3588 SoC based boards. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block. Add just the basic support for now, i.e. RGB output up to 4K@60Hz, without audio, CEC or any of the HDMI 2.1 specific features. Co-developed-by:
Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller supports the following features, among others: * Fixed Rate Link (FRL) * 4K@120Hz and 8K@60Hz video modes * Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka Cinema VRR * Fast Vactive (FVA), aka Quick Frame Transport (QFT) * SCDC I2C DDC access * TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 * YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds * Multi-stream audio * Enhanced Audio Return Channel (EARC) Add driver to enable basic support, i.e. RGB output up to 4K@60Hz, without audio, CEC or any HDMI 2.1 specific features. Co-developed-by:
Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX controller. Since this is a new IP block, quite different from those used in the previous generations of Rockchip SoCs, add a new binding file for it. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Add dt-binding schema containing the common properties for the Synopsys DesignWare HDMI QP TX controller. Note this is not a full dt-binding specification, but is meant to be referenced by platform-specific bindings for this IP core. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Driver makes use of the BIT() macro, but relies on the bits header being implicitly included. Explicitly pull the header in to avoid potential build failures in some configurations. While at it, reorder include directives alphabetically. Fixes: 8c854654 ("drm/rockchip: move output interface related definition to rockchip_drm_drv.h") Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The recent switch to drmm allocation in drm_bridge_connector_init() may cause double free on bridge_connector in some of the error handling paths. Drop the explicit kfree() calls on bridge_connector. Fixes: c12907be ("drm/bridge-connector: switch to using drmm allocations") Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of the HDMI0 PHY PLL to support the additional display modes. Note this requires commit "drm/rockchip: vop2: Improve display modes handling on rk3588", which needs a rework to be upstreamable. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The HDMI0 PHY can be used as a clock provider on RK3588, hence add the missing #clock-cells property.
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Add the necessary DT changes to enable HDMI0 on Rockchip RK3588 EVB1. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Add the necessary DT changes to enable HDMI0 on Rock 5B. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Add DT node for the HDMI0 bridge found on RK3588 SoC. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The initial vop2 support for rk3588 in mainline is not able to handle all display modes supported by connected displays, e.g. 2560x1440-75.00Hz, 2048x1152-60.00Hz, 1024x768-60.00Hz. Additionally, it doesn't cope with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Improve HDMI0 clocking in order to support the additional display modes. Fixes: 5a028e8f ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
Allow using the clock provided by HDMI0 PHY PLL to improve HDMI output support on RK3588 SoC. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
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For upstreaming, this requires extending the standard PHY API to support HDMI configuration options [1]. Currently, the bus_width PHY attribute is used to pass clock rate and flags for 10-bit color depth, FRL and EARC. This is done by the HDMI bridge driver via phy_set_bus_width(). [1]: https://lore.kernel.org/all/20240306101625.795732-3-alexander.stein@ew.tq-group.com/ Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add the necessary '#clock-cells' property. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> -
When a new PHY is created via [devm_]phy_create(), the runtime PM for it is not enabled unless the parent device (which creates the PHY) has its own runtime PM already enabled. Move the call to devm_pm_runtime_enable() before devm_phy_create() to enable runtime PM at PHY core level. With this change the ->power_on() and ->power_off() callbacks do not require explicit runtime PM management anymore, since the PHY core handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and phy_power_off() are invoked. Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and pm_runtime_put() helpers. Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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