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hardware-enablement / Rockchip upstream enablement efforts / linux
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Sebastian Reichel
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If clk_round_rate(clk, ULONG_MAX) is called to acquire the highest
available clock rate and the highest available clock rate is smaller
than ULONG_MAX/2, the result of "req->rate - tmp_req.rate" has the
highest bit set. Since the input to abs() is signed, that means the
number will be miss-interpreted.
This results in the logic being reverted and the worst choice being
selected as the best one. For example this has been observed on RK3588
for the eMMC clock:
GPLL: abs(18446744073709551615 - 1188000000) = 1188000001
CPLL: abs(18446744073709551615 - 1500000000) = 1500000001
XIN24M: abs(18446744073709551615 - 24000000) = 24000001
With the updated logic any casting between signed and unsigned is
avoided and the numbers look like this instead:
GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615
CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615
XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615
As a result the parent with the highest acceptable rate is chosen
instead of the parent clock with the lowest one.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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