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Commit 240c9944 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli
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arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes


Thanks to Heiko's work getting OTP working on the RK3576, we can specify
the thermal sensor trim values which are stored there now, and with my
driver addition to rockchip_thermal, we can make use of these.

Add them to the devicetree for the SoC.

Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
parent 9db5a8ef
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......@@ -1465,6 +1465,30 @@ gpu_leakage: gpu-leakage@21 {
log_leakage: log-leakage@22 {
reg = <0x22 0x1>;
};
bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
reg = <0x24 0x2>;
bits = <0 10>;
};
litcore_tsadc_trim: litcore-tsadc-trim@26 {
reg = <0x26 0x2>;
bits = <0 10>;
};
ddr_tsadc_trim: ddr-tsadc-trim@28 {
reg = <0x28 0x2>;
bits = <0 10>;
};
npu_tsadc_trim: npu-tsadc-trim@2a {
reg = <0x2a 0x2>;
bits = <0 10>;
};
gpu_tsadc_trim: gpu-tsadc-trim@2c {
reg = <0x2c 0x2>;
bits = <0 10>;
};
soc_tsadc_trim: soc-tsadc-trim@64 {
reg = <0x64 0x2>;
bits = <0 10>;
};
};
gic: interrupt-controller@2a701000 {
......@@ -1876,6 +1900,39 @@ tsadc: tsadc@2ae70000 {
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
#address-cells = <1>;
#size-cells = <0>;
sensor@0 {
reg = <0>;
nvmem-cells = <&soc_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@1 {
reg = <1>;
nvmem-cells = <&bigcore_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@2 {
reg = <2>;
nvmem-cells = <&litcore_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@3 {
reg = <3>;
nvmem-cells = <&ddr_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@4 {
reg = <4>;
nvmem-cells = <&npu_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@5 {
reg = <5>;
nvmem-cells = <&gpu_tsadc_trim>;
nvmem-cell-names = "trim";
};
};
i2c9: i2c@2ae80000 {
......
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