README

		which has to be defined in a board specific file

- ATAPI Support:
		CONFIG_ATAPI

		Set this to enable ATAPI support.

- LBA48 Support
		CONFIG_LBA48

		Set this to enable support for disks larger than 137GB
		Also look at CONFIG_SYS_64BIT_LBA.
		Whithout these , LBA48 support uses 32bit variables and will 'only'
		support disks up to 2.1TB.

		CONFIG_SYS_64BIT_LBA:
			When enabled, makes the IDE subsystem use 64bit sector addresses.
			Default is 32bit.

- SCSI Support:
		At the moment only there is only support for the
		SYM53C8XX SCSI controller; define
		CONFIG_SCSI_SYM53C8XX to enable it.

		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
		maximum numbers of LUNs, SCSI ID's and target
		devices.
		CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)

- NETWORK Support (PCI):
		CONFIG_E1000
		Support for Intel 8254x/8257x gigabit chips.

		CONFIG_E1000_SPI
		Utility code for direct access to the SPI bus on Intel 8257x.
		This does not do anything useful unless you set at least one
		of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.

		CONFIG_E1000_SPI_GENERIC
		Allow generic access to the SPI bus on the Intel 8257x, for
		example with the "sspi" command.

		CONFIG_CMD_E1000
		Management command for E1000 devices.  When used on devices
		with SPI support you can reprogram the EEPROM from U-Boot.

		CONFIG_E1000_FALLBACK_MAC
		default MAC for empty EEPROM after production.

		CONFIG_EEPRO100
		Support for Intel 82557/82559/82559ER chips.
		Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
		write routine for first time initialisation.

		CONFIG_TULIP
		Support for Digital 2114x chips.
		Optional CONFIG_TULIP_SELECT_MEDIA for board specific
		modem chip initialisation (KS8761/QS6611).

		CONFIG_NATSEMI
		Support for National dp83815 chips.

		CONFIG_NS8382X
		Support for National dp8382[01] gigabit chips.

- NETWORK Support (other):

		CONFIG_DRIVER_AT91EMAC
		Support for AT91RM9200 EMAC.

			CONFIG_RMII
			Define this to use reduced MII inteface

			CONFIG_DRIVER_AT91EMAC_QUIET
			If this defined, the driver is quiet.
			The driver doen't show link status messages.

		CONFIG_CALXEDA_XGMAC
		Support for the Calxeda XGMAC device

		CONFIG_DRIVER_LAN91C96
		Support for SMSC's LAN91C96 chips.

			CONFIG_LAN91C96_BASE
			Define this to hold the physical address
			of the LAN91C96's I/O space

			CONFIG_LAN91C96_USE_32_BIT
			Define this to enable 32 bit addressing

		CONFIG_DRIVER_SMC91111
		Support for SMSC's LAN91C111 chip

			CONFIG_SMC91111_BASE
			Define this to hold the physical address
			of the device (I/O space)

			CONFIG_SMC_USE_32_BIT
			Define this if data bus is 32 bits

			CONFIG_SMC_USE_IOFUNCS
			Define this to use i/o functions instead of macros
			(some hardware wont work with macros)

		CONFIG_DRIVER_TI_EMAC
		Support for davinci emac

			CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
			Define this if you have more then 3 PHYs.

		CONFIG_FTGMAC100
		Support for Faraday's FTGMAC100 Gigabit SoC Ethernet

			CONFIG_FTGMAC100_EGIGA
			Define this to use GE link update with gigabit PHY.
			Define this if FTGMAC100 is connected to gigabit PHY.
			If your system has 10/100 PHY only, it might not occur
			wrong behavior. Because PHY usually return timeout or
			useless data when polling gigabit status and gigabit
			control registers. This behavior won't affect the
			correctnessof 10/100 link speed update.

		CONFIG_SMC911X
		Support for SMSC's LAN911x and LAN921x chips

			CONFIG_SMC911X_BASE
			Define this to hold the physical address
			of the device (I/O space)

			CONFIG_SMC911X_32_BIT
			Define this if data bus is 32 bits

			CONFIG_SMC911X_16_BIT
			Define this if data bus is 16 bits. If your processor
			automatically converts one 32 bit word to two 16 bit
			words you may also try CONFIG_SMC911X_32_BIT.

		CONFIG_SH_ETHER
		Support for Renesas on-chip Ethernet controller

			CONFIG_SH_ETHER_USE_PORT
			Define the number of ports to be used

			CONFIG_SH_ETHER_PHY_ADDR
			Define the ETH PHY's address

			CONFIG_SH_ETHER_CACHE_WRITEBACK
			If this option is set, the driver enables cache flush.

- TPM Support:
		CONFIG_GENERIC_LPC_TPM
		Support for generic parallel port TPM devices. Only one device
		per system is supported at this time.

			CONFIG_TPM_TIS_BASE_ADDRESS
			Base address where the generic TPM device is mapped
			to. Contemporary x86 systems usually map it at
			0xfed40000.

- USB Support:
		At the moment only the UHCI host controller is
		supported (PIP405, MIP405, MPC5200); define
		CONFIG_USB_UHCI to enable it.
		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
		and define CONFIG_USB_STORAGE to enable the USB
		storage devices.
		Note:
		Supported are USB Keyboards and USB Floppy drives
		(TEAC FD-05PUB).
		MPC5200 USB requires additional defines:
			CONFIG_USB_CLOCK
				for 528 MHz Clock: 0x0001bbbb
			CONFIG_PSC3_USB
				for USB on PSC3
			CONFIG_USB_CONFIG
				for differential drivers: 0x00001000
				for single ended drivers: 0x00005000
				for differential drivers on PSC3: 0x00000100
				for single ended drivers on PSC3: 0x00004100
			CONFIG_SYS_USB_EVENT_POLL
				May be defined to allow interrupt polling
				instead of using asynchronous interrupts

		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
		txfilltuning field in the EHCI controller on reset.

- USB Device:
		Define the below if you wish to use the USB console.
		Once firmware is rebuilt from a serial console issue the
		command "setenv stdin usbtty; setenv stdout usbtty" and
		attach your USB cable. The Unix command "dmesg" should print
		it has found a new device. The environment variable usbtty
		can be set to gserial or cdc_acm to enable your device to
		appear to a USB host as a Linux gserial device or a
		Common Device Class Abstract Control Model serial device.
		If you select usbtty = gserial you should be able to enumerate
		a Linux host by
		# modprobe usbserial vendor=0xVendorID product=0xProductID
		else if using cdc_acm, simply setting the environment
		variable usbtty to be cdc_acm should suffice. The following
		might be defined in YourBoardName.h

			CONFIG_USB_DEVICE
			Define this to build a UDC device

			CONFIG_USB_TTY
			Define this to have a tty type of device available to
			talk to the UDC device

			CONFIG_USBD_HS
			Define this to enable the high speed support for usb
			device and usbtty. If this feature is enabled, a routine
			int is_usbd_high_speed(void)
			also needs to be defined by the driver to dynamically poll
			whether the enumeration has succeded at high speed or full
			speed.

			CONFIG_SYS_CONSOLE_IS_IN_ENV
			Define this if you want stdin, stdout &/or stderr to
			be set to usbtty.

			mpc8xx:
				CONFIG_SYS_USB_EXTC_CLK 0xBLAH
				Derive USB clock from external clock "blah"
				- CONFIG_SYS_USB_EXTC_CLK 0x02

				CONFIG_SYS_USB_BRG_CLK 0xBLAH
				Derive USB clock from brgclk
				- CONFIG_SYS_USB_BRG_CLK 0x04

		If you have a USB-IF assigned VendorID then you may wish to
		define your own vendor specific values either in BoardName.h
		or directly in usbd_vendor_info.h. If you don't define
		CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
		CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
		should pretend to be a Linux device to it's target host.

			CONFIG_USBD_MANUFACTURER
			Define this string as the name of your company for
			- CONFIG_USBD_MANUFACTURER "my company"

			CONFIG_USBD_PRODUCT_NAME
			Define this string as the name of your product
			- CONFIG_USBD_PRODUCT_NAME "acme usb device"

			CONFIG_USBD_VENDORID
			Define this as your assigned Vendor ID from the USB
			Implementors Forum. This *must* be a genuine Vendor ID
			to avoid polluting the USB namespace.
			- CONFIG_USBD_VENDORID 0xFFFF

			CONFIG_USBD_PRODUCTID
			Define this as the unique Product ID
			for your device
			- CONFIG_USBD_PRODUCTID 0xFFFF

- ULPI Layer Support:
		The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
		the generic ULPI layer. The generic layer accesses the ULPI PHY
		via the platform viewport, so you need both the genric layer and
		the viewport enabled. Currently only Chipidea/ARC based
		viewport is supported.
		To enable the ULPI layer support, define CONFIG_USB_ULPI and
		CONFIG_USB_ULPI_VIEWPORT in your board configuration file.

- MMC Support:
		The MMC controller on the Intel PXA is supported. To
		enable this define CONFIG_MMC. The MMC can be
		accessed from the boot prompt by mapping the device
		to physical memory similar to flash. Command line is
		enabled with CONFIG_CMD_MMC. The MMC driver also works with
		the FAT fs. This is enabled with CONFIG_CMD_FAT.

		CONFIG_SH_MMCIF
		Support for Renesas on-chip MMCIF controller

			CONFIG_SH_MMCIF_ADDR
			Define the base address of MMCIF registers

			CONFIG_SH_MMCIF_CLK
			Define the clock frequency for MMCIF

- Journaling Flash filesystem support:
		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
		CONFIG_JFFS2_NAND_DEV
		Define these for a default partition on a NAND device

		CONFIG_SYS_JFFS2_FIRST_SECTOR,
		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
		Define these for a default partition on a NOR device

		CONFIG_SYS_JFFS_CUSTOM_PART
		Define this to create an own partition. You have to provide a
		function struct part_info* jffs2_part_info(int part_num)

		If you define only one JFFS2 partition you may also want to
		#define CONFIG_SYS_JFFS_SINGLE_PART	1
		to disable the command chpart. This is the default when you
		have not defined a custom partition

- FAT(File Allocation Table) filesystem write function support:
		CONFIG_FAT_WRITE

		Define this to enable support for saving memory data as a
		file in FAT formatted partition.

		This will also enable the command "fatwrite" enabling the
		user to write files to FAT.

- Keyboard Support:
		CONFIG_ISA_KEYBOARD

		Define this to enable standard (PC-Style) keyboard
		support

		CONFIG_I8042_KBD
		Standard PC keyboard driver with US (is default) and
		GERMAN key layout (switch via environment 'keymap=de') support.
		Export function i8042_kbd_init, i8042_tstc and i8042_getc
		for cfb_console. Supports cursor blinking.

- Video support:
		CONFIG_VIDEO

		Define this to enable video support (for output to
		video).

		CONFIG_VIDEO_CT69000

		Enable Chips & Technologies 69000 Video chip

		CONFIG_VIDEO_SMI_LYNXEM
		Enable Silicon Motion SMI 712/710/810 Video chip. The
		video output is selected via environment 'videoout'
		(1 = LCD and 2 = CRT). If videoout is undefined, CRT is
		assumed.

		For the CT69000 and SMI_LYNXEM drivers, videomode is
		selected via environment 'videomode'. Two different ways
		are possible:
		- "videomode=num"   'num' is a standard LiLo mode numbers.
		Following standard modes are supported	(* is default):

		      Colors	640x480 800x600 1024x768 1152x864 1280x1024
		-------------+---------------------------------------------
		      8 bits |	0x301*	0x303	 0x305	  0x161	    0x307
		     15 bits |	0x310	0x313	 0x316	  0x162	    0x319
		     16 bits |	0x311	0x314	 0x317	  0x163	    0x31A
		     24 bits |	0x312	0x315	 0x318	    ?	    0x31B
		-------------+---------------------------------------------
		(i.e. setenv videomode 317; saveenv; reset;)

		- "videomode=bootargs" all the video parameters are parsed
		from the bootargs. (See drivers/video/videomodes.c)


		CONFIG_VIDEO_SED13806
		Enable Epson SED13806 driver. This driver supports 8bpp
		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
		or CONFIG_VIDEO_SED13806_16BPP

		CONFIG_FSL_DIU_FB
		Enable the Freescale DIU video driver.	Reference boards for
		SOCs that have a DIU should define this macro to enable DIU
		support, and should also define these other macros:

			CONFIG_SYS_DIU_ADDR
			CONFIG_VIDEO
			CONFIG_CMD_BMP
			CONFIG_CFB_CONSOLE
			CONFIG_VIDEO_SW_CURSOR
			CONFIG_VGA_AS_SINGLE_DEVICE
			CONFIG_VIDEO_LOGO
			CONFIG_VIDEO_BMP_LOGO

		The DIU driver will look for the 'video-mode' environment
		variable, and if defined, enable the DIU as a console during
		boot.  See the documentation file README.video for a
		description of this variable.

- Keyboard Support:
		CONFIG_KEYBOARD

		Define this to enable a custom keyboard support.
		This simply calls drv_keyboard_init() which must be
		defined in your board-specific files.
		The only board using this so far is RBC823.

- LCD Support:	CONFIG_LCD

		Define this to enable LCD support (for output to LCD
		display); also select one of the supported displays
		by defining one of these:

		CONFIG_ATMEL_LCD:

			HITACHI TX09D70VM1CCA, 3.5", 240x320.

		CONFIG_NEC_NL6448AC33:

			NEC NL6448AC33-18. Active, color, single scan.

		CONFIG_NEC_NL6448BC20

			NEC NL6448BC20-08. 6.5", 640x480.
			Active, color, single scan.

		CONFIG_NEC_NL6448BC33_54

			NEC NL6448BC33-54. 10.4", 640x480.
			Active, color, single scan.

		CONFIG_SHARP_16x9

			Sharp 320x240. Active, color, single scan.
			It isn't 16x9, and I am not sure what it is.

		CONFIG_SHARP_LQ64D341

			Sharp LQ64D341 display, 640x480.
			Active, color, single scan.

		CONFIG_HLD1045

			HLD1045 display, 640x480.
			Active, color, single scan.

		CONFIG_OPTREX_BW

			Optrex	 CBL50840-2 NF-FW 99 22 M5
			or
			Hitachi	 LMG6912RPFC-00T
			or
			Hitachi	 SP14Q002

			320x240. Black & white.

		Normally display is black on white background; define
		CONFIG_SYS_WHITE_ON_BLACK to get it inverted.

- Splash Screen Support: CONFIG_SPLASH_SCREEN

		If this option is set, the environment is checked for
		a variable "splashimage". If found, the usual display
		of logo, copyright and system information on the LCD
		is suppressed and the BMP image at the address
		specified in "splashimage" is loaded instead. The
		console is redirected to the "nulldev", too. This
		allows for a "silent" boot where a splash screen is
		loaded very quickly after power-on.

		CONFIG_SPLASH_SCREEN_ALIGN

		If this option is set the splash image can be freely positioned
		on the screen. Environment variable "splashpos" specifies the
		position as "x,y". If a positive number is given it is used as
		number of pixel from left/top. If a negative number is given it
		is used as number of pixel from right/bottom. You can also
		specify 'm' for centering the image.

		Example:
		setenv splashpos m,m
			=> image at center of screen

		setenv splashpos 30,20
			=> image at x = 30 and y = 20

		setenv splashpos -10,m
			=> vertically centered image
			   at x = dspWidth - bmpWidth - 9

- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP

		If this option is set, additionally to standard BMP
		images, gzipped BMP images can be displayed via the
		splashscreen support or the bmp command.

- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8

		If this option is set, 8-bit RLE compressed BMP images
		can be displayed via the splashscreen support or the
		bmp command.

- Compression support:
		CONFIG_BZIP2

		If this option is set, support for bzip2 compressed
		images is included. If not, only uncompressed and gzip
		compressed images are supported.

		NOTE: the bzip2 algorithm requires a lot of RAM, so
		the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
		be at least 4MB.

		CONFIG_LZMA

		If this option is set, support for lzma compressed
		images is included.

		Note: The LZMA algorithm adds between 2 and 4KB of code and it
		requires an amount of dynamic memory that is given by the
		formula:

			(1846 + 768 << (lc + lp)) * sizeof(uint16)

		Where lc and lp stand for, respectively, Literal context bits
		and Literal pos bits.

		This value is upper-bounded by 14MB in the worst case. Anyway,
		for a ~4MB large kernel image, we have lc=3 and lp=0 for a
		total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
		a very small buffer.

		Use the lzmainfo tool to determinate the lc and lp values and
		then calculate the amount of needed dynamic memory (ensuring
		the appropriate CONFIG_SYS_MALLOC_LEN value).

- MII/PHY support:
		CONFIG_PHY_ADDR

		The address of PHY on MII bus.

		CONFIG_PHY_CLOCK_FREQ (ppc4xx)

		The clock frequency of the MII bus

		CONFIG_PHY_GIGE

		If this option is set, support for speed/duplex
		detection of gigabit PHY is included.

		CONFIG_PHY_RESET_DELAY

		Some PHY like Intel LXT971A need extra delay after
		reset before any MII register access is possible.
		For such PHY, set this option to the usec delay
		required. (minimum 300usec for LXT971A)

		CONFIG_PHY_CMD_DELAY (ppc4xx)

		Some PHY like Intel LXT971A need extra delay after
		command issued before MII status register can be read

- Ethernet address:
		CONFIG_ETHADDR
		CONFIG_ETH1ADDR
		CONFIG_ETH2ADDR
		CONFIG_ETH3ADDR
		CONFIG_ETH4ADDR
		CONFIG_ETH5ADDR

		Define a default value for Ethernet address to use
		for the respective Ethernet interface, in case this
		is not determined automatically.

- IP address:
		CONFIG_IPADDR

		Define a default value for the IP address to use for
		the default Ethernet interface, in case this is not
		determined through e.g. bootp.
		(Environment variable "ipaddr")

- Server IP address:
		CONFIG_SERVERIP

		Defines a default value for the IP address of a TFTP
		server to contact when using the "tftboot" command.
		(Environment variable "serverip")

		CONFIG_KEEP_SERVERADDR

		Keeps the server's MAC address, in the env 'serveraddr'
		for passing to bootargs (like Linux's netconsole option)

- Gateway IP address:
		CONFIG_GATEWAYIP

		Defines a default value for the IP address of the
		default router where packets to other networks are
		sent to.
		(Environment variable "gatewayip")

- Subnet mask:
		CONFIG_NETMASK

		Defines a default value for the subnet mask (or
		routing prefix) which is used to determine if an IP
		address belongs to the local subnet or needs to be
		forwarded through a router.
		(Environment variable "netmask")

- Multicast TFTP Mode:
		CONFIG_MCAST_TFTP

		Defines whether you want to support multicast TFTP as per
		rfc-2090; for example to work with atftp.  Lets lots of targets
		tftp down the same boot image concurrently.  Note: the Ethernet
		driver in use must provide a function: mcast() to join/leave a
		multicast group.

- BOOTP Recovery Mode:
		CONFIG_BOOTP_RANDOM_DELAY

		If you have many targets in a network that try to
		boot using BOOTP, you may want to avoid that all
		systems send out BOOTP requests at precisely the same
		moment (which would happen for instance at recovery
		from a power failure, when all systems will try to
		boot, thus flooding the BOOTP server. Defining
		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
		inserted before sending out BOOTP requests. The
		following delays are inserted then:

		1st BOOTP request:	delay 0 ... 1 sec
		2nd BOOTP request:	delay 0 ... 2 sec
		3rd BOOTP request:	delay 0 ... 4 sec
		4th and following
		BOOTP requests:		delay 0 ... 8 sec

- DHCP Advanced Options:
		You can fine tune the DHCP functionality by defining
		CONFIG_BOOTP_* symbols:

		CONFIG_BOOTP_SUBNETMASK
		CONFIG_BOOTP_GATEWAY
		CONFIG_BOOTP_HOSTNAME
		CONFIG_BOOTP_NISDOMAIN
		CONFIG_BOOTP_BOOTPATH
		CONFIG_BOOTP_BOOTFILESIZE
		CONFIG_BOOTP_DNS
		CONFIG_BOOTP_DNS2
		CONFIG_BOOTP_SEND_HOSTNAME
		CONFIG_BOOTP_NTPSERVER
		CONFIG_BOOTP_TIMEOFFSET
		CONFIG_BOOTP_VENDOREX
		CONFIG_BOOTP_MAY_FAIL

		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
		environment variable, not the BOOTP server.

		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
		after the configured retry count, the call will fail
		instead of starting over.  This can be used to fail over
		to Link-local IP address configuration if the DHCP server
		is not available.

		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
		serverip from a DHCP server, it is possible that more
		than one DNS serverip is offered to the client.
		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
		serverip will be stored in the additional environment
		variable "dnsip2". The first DNS serverip is always
		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
		is defined.

		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
		to do a dynamic update of a DNS server. To do this, they
		need the hostname of the DHCP requester.
		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
		of the "hostname" environment variable is passed as
		option 12 to the DHCP server.

		CONFIG_BOOTP_DHCP_REQUEST_DELAY

		A 32bit value in microseconds for a delay between
		receiving a "DHCP Offer" and sending the "DHCP Request".
		This fixes a problem with certain DHCP servers that don't
		respond 100% of the time to a "DHCP request". E.g. On an
		AT91RM9200 processor running at 180MHz, this delay needed
		to be *at least* 15,000 usec before a Windows Server 2003
		DHCP server would reply 100% of the time. I recommend at
		least 50,000 usec to be safe. The alternative is to hope
		that one of the retries will be successful but note that
		the DHCP timeout and retry process takes a longer than
		this delay.

 - Link-local IP address negotiation:
		Negotiate with other link-local clients on the local network
		for an address that doesn't require explicit configuration.
		This is especially useful if a DHCP server cannot be guaranteed
		to exist in all environments that the device must operate.

		See doc/README.link-local for more information.

 - CDP Options:
		CONFIG_CDP_DEVICE_ID

		The device id used in CDP trigger frames.

		CONFIG_CDP_DEVICE_ID_PREFIX

		A two character string which is prefixed to the MAC address
		of the device.

		CONFIG_CDP_PORT_ID

		A printf format string which contains the ascii name of
		the port. Normally is set to "eth%d" which sets
		eth0 for the first Ethernet, eth1 for the second etc.

		CONFIG_CDP_CAPABILITIES

		A 32bit integer which indicates the device capabilities;
		0x00000010 for a normal host which does not forwards.

		CONFIG_CDP_VERSION

		An ascii string containing the version of the software.

		CONFIG_CDP_PLATFORM

		An ascii string containing the name of the platform.

		CONFIG_CDP_TRIGGER

		A 32bit integer sent on the trigger.

		CONFIG_CDP_POWER_CONSUMPTION

		A 16bit integer containing the power consumption of the
		device in .1 of milliwatts.

		CONFIG_CDP_APPLIANCE_VLAN_TYPE

		A byte containing the id of the VLAN.

- Status LED:	CONFIG_STATUS_LED

		Several configurations allow to display the current
		status using a LED. For instance, the LED will blink
		fast while running U-Boot code, stop blinking as
		soon as a reply to a BOOTP request was received, and
		start blinking slow once the Linux kernel is running
		(supported by a status LED driver in the Linux
		kernel). Defining CONFIG_STATUS_LED enables this
		feature in U-Boot.

- CAN Support:	CONFIG_CAN_DRIVER

		Defining CONFIG_CAN_DRIVER enables CAN driver support
		on those systems that support this (optional)
		feature, like the TQM8xxL modules.

- I2C Support:	CONFIG_HARD_I2C | CONFIG_SOFT_I2C

		These enable I2C serial bus commands. Defining either of
		(but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will
		include the appropriate I2C driver for the selected CPU.

		This will allow you to use i2c commands at the u-boot
		command line (as long as you set CONFIG_CMD_I2C in
		CONFIG_COMMANDS) and communicate with i2c based realtime
		clock chips. See common/cmd_i2c.c for a description of the
		command line interface.

		CONFIG_HARD_I2C selects a hardware I2C controller.

		CONFIG_SOFT_I2C configures u-boot to use a software (aka
		bit-banging) driver instead of CPM or similar hardware
		support for I2C.

		There are several other quantities that must also be
		defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.

		In both cases you will need to define CONFIG_SYS_I2C_SPEED
		to be the frequency (in Hz) at which you wish your i2c bus
		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
		the CPU's i2c node address).

		Now, the u-boot i2c code for the mpc8xx
		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
		and so its address should therefore be cleared to 0 (See,
		eg, MPC823e User's Manual p.16-473). So, set
		CONFIG_SYS_I2C_SLAVE to 0.

		CONFIG_SYS_I2C_INIT_MPC5XXX

		When a board is reset during an i2c bus transfer
		chips might think that the current transfer is still
		in progress.  Reset the slave devices by sending start
		commands until the slave device responds.

		That's all that's required for CONFIG_HARD_I2C.

		If you use the software i2c interface (CONFIG_SOFT_I2C)
		then the following macros need to be defined (examples are
		from include/configs/lwmon.h):

		I2C_INIT

		(Optional). Any commands necessary to enable the I2C
		controller or configure ports.

		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)

		I2C_PORT

		(Only for MPC8260 CPU). The I/O port to use (the code
		assumes both bits are on the same port). Valid values
		are 0..3 for ports A..D.

		I2C_ACTIVE

		The code necessary to make the I2C data line active
		(driven).  If the data line is open collector, this
		define can be null.

		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)

		I2C_TRISTATE

		The code necessary to make the I2C data line tri-stated
		(inactive).  If the data line is open collector, this
		define can be null.

		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)

		I2C_READ

		Code that returns TRUE if the I2C data line is high,
		FALSE if it is low.

		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)

		I2C_SDA(bit)

		If <bit> is TRUE, sets the I2C data line high. If it
		is FALSE, it clears it (low).

		eg: #define I2C_SDA(bit) \
			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA

		I2C_SCL(bit)

		If <bit> is TRUE, sets the I2C clock line high. If it
		is FALSE, it clears it (low).

		eg: #define I2C_SCL(bit) \
			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL

		I2C_DELAY

		This delay is invoked four times per clock cycle so this
		controls the rate of data transfer.  The data rate thus
		is 1 / (I2C_DELAY * 4). Often defined to be something
		like:

		#define I2C_DELAY  udelay(2)

		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA

		If your arch supports the generic GPIO framework (asm/gpio.h),
		then you may alternatively define the two GPIOs that are to be
		used as SCL / SDA.  Any of the previous I2C_xxx macros will
		have GPIO-based defaults assigned to them as appropriate.

		You should define these to the GPIO value as given directly to
		the generic GPIO functions.

		CONFIG_SYS_I2C_INIT_BOARD

		When a board is reset during an i2c bus transfer
		chips might think that the current transfer is still
		in progress. On some boards it is possible to access
		the i2c SCLK line directly, either by using the
		processor pin as a GPIO or by having a second pin
		connected to the bus. If this option is defined a
		custom i2c_init_board() routine in boards/xxx/board.c
		is run early in the boot sequence.

		CONFIG_SYS_I2C_BOARD_LATE_INIT

		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
		defined a custom i2c_board_late_init() routine in
		boards/xxx/board.c is run AFTER the operations in i2c_init()
		is completed. This callpoint can be used to unreset i2c bus
		using CPU i2c controller register accesses for CPUs whose i2c
		controller provide such a method. It is called at the end of
		i2c_init() to allow i2c_init operations to setup the i2c bus
		controller on the CPU (e.g. setting bus speed & slave address).

		CONFIG_I2CFAST (PPC405GP|PPC405EP only)

		This option enables configuration of bi_iic_fast[] flags
		in u-boot bd_info structure based on u-boot environment
		variable "i2cfast". (see also i2cfast)

		CONFIG_I2C_MULTI_BUS

		This option allows the use of multiple I2C buses, each of which
		must have a controller.	 At any point in time, only one bus is
		active.	 To switch to a different bus, use the 'i2c dev' command.
		Note that bus numbering is zero-based.

		CONFIG_SYS_I2C_NOPROBES

		This option specifies a list of I2C devices that will be skipped
		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
		is set, specify a list of bus-device pairs.  Otherwise, specify
		a 1D array of device addresses

		e.g.
			#undef	CONFIG_I2C_MULTI_BUS
			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}

		will skip addresses 0x50 and 0x68 on a board with one I2C bus

			#define CONFIG_I2C_MULTI_BUS
			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}

		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1

		CONFIG_SYS_SPD_BUS_NUM

		If defined, then this indicates the I2C bus number for DDR SPD.
		If not defined, then U-Boot assumes that SPD is on I2C bus 0.

		CONFIG_SYS_RTC_BUS_NUM

		If defined, then this indicates the I2C bus number for the RTC.
		If not defined, then U-Boot assumes that RTC is on I2C bus 0.

		CONFIG_SYS_DTT_BUS_NUM

		If defined, then this indicates the I2C bus number for the DTT.
		If not defined, then U-Boot assumes that DTT is on I2C bus 0.

		CONFIG_SYS_I2C_DTT_ADDR:

		If defined, specifies the I2C address of the DTT device.
		If not defined, then U-Boot uses predefined value for
		specified DTT device.

		CONFIG_FSL_I2C

		Define this option if you want to use Freescale's I2C driver in
		drivers/i2c/fsl_i2c.c.

		CONFIG_I2C_MUX

		Define this option if you have I2C devices reached over 1 .. n
		I2C Muxes like the pca9544a. This option addes a new I2C
		Command "i2c bus [muxtype:muxaddr:muxchannel]" which adds a
		new I2C Bus to the existing I2C Busses. If you select the
		new Bus with "i2c dev", u-bbot sends first the commandos for
		the muxes to activate this new "bus".

		CONFIG_I2C_MULTI_BUS must be also defined, to use this
		feature!

		Example:
		Adding a new I2C Bus reached over 2 pca9544a muxes
			The First mux with address 70 and channel 6
			The Second mux with address 71 and channel 4

		=> i2c bus pca9544a:70:6:pca9544a:71:4

		Use the "i2c bus" command without parameter, to get a list
		of I2C Busses with muxes:

		=> i2c bus
		Busses reached over muxes:
		Bus ID: 2
		  reached over Mux(es):
		    pca9544a@70 ch: 4
		Bus ID: 3
		  reached over Mux(es):
		    pca9544a@70 ch: 6
		    pca9544a@71 ch: 4
		=>

		If you now switch to the new I2C Bus 3 with "i2c dev 3"
		u-boot first sends the command to the mux@70 to enable
		channel 6, and then the command to the mux@71 to enable
		the channel 4.

		After that, you can use the "normal" i2c commands as
		usual to communicate with your I2C devices behind
		the 2 muxes.

		This option is actually implemented for the bitbanging
		algorithm in common/soft_i2c.c and for the Hardware I2C
		Bus on the MPC8260. But it should be not so difficult
		to add this option to other architectures.

		CONFIG_SOFT_I2C_READ_REPEATED_START

		defining this will force the i2c_read() function in
		the soft_i2c driver to perform an I2C repeated start
		between writing the address pointer and reading the
		data.  If this define is omitted the default behaviour
		of doing a stop-start sequence will be used.  Most I2C
		devices can use either method, but some require one or
		the other.