README

		CONFIG_GATEWAYIP

		Defines a default value for the IP address of the
		default router where packets to other networks are
		sent to.
		(Environment variable "gatewayip")

- Subnet mask:
		CONFIG_NETMASK

		Defines a default value for the subnet mask (or
		routing prefix) which is used to determine if an IP
		address belongs to the local subnet or needs to be
		forwarded through a router.
		(Environment variable "netmask")

- Multicast TFTP Mode:
		CONFIG_MCAST_TFTP

		Defines whether you want to support multicast TFTP as per
		rfc-2090; for example to work with atftp.  Lets lots of targets
		tftp down the same boot image concurrently.  Note: the Ethernet
		driver in use must provide a function: mcast() to join/leave a
		multicast group.

- BOOTP Recovery Mode:
		CONFIG_BOOTP_RANDOM_DELAY

		If you have many targets in a network that try to
		boot using BOOTP, you may want to avoid that all
		systems send out BOOTP requests at precisely the same
		moment (which would happen for instance at recovery
		from a power failure, when all systems will try to
		boot, thus flooding the BOOTP server. Defining
		CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be
		inserted before sending out BOOTP requests. The
		following delays are inserted then:

		1st BOOTP request:	delay 0 ... 1 sec
		2nd BOOTP request:	delay 0 ... 2 sec
		3rd BOOTP request:	delay 0 ... 4 sec
		4th and following
		BOOTP requests:		delay 0 ... 8 sec

		CONFIG_BOOTP_ID_CACHE_SIZE

		BOOTP packets are uniquely identified using a 32-bit ID. The
		server will copy the ID from client requests to responses and
		U-Boot will use this to determine if it is the destination of
		an incoming response. Some servers will check that addresses
		aren't in use before handing them out (usually using an ARP
		ping) and therefore take up to a few hundred milliseconds to
		respond. Network congestion may also influence the time it
		takes for a response to make it back to the client. If that
		time is too long, U-Boot will retransmit requests. In order
		to allow earlier responses to still be accepted after these
		retransmissions, U-Boot's BOOTP client keeps a small cache of
		IDs. The CONFIG_BOOTP_ID_CACHE_SIZE controls the size of this
		cache. The default is to keep IDs for up to four outstanding
		requests. Increasing this will allow U-Boot to accept offers
		from a BOOTP client in networks with unusually high latency.

- DHCP Advanced Options:
		You can fine tune the DHCP functionality by defining
		CONFIG_BOOTP_* symbols:

		CONFIG_BOOTP_SUBNETMASK
		CONFIG_BOOTP_GATEWAY
		CONFIG_BOOTP_HOSTNAME
		CONFIG_BOOTP_NISDOMAIN
		CONFIG_BOOTP_BOOTPATH
		CONFIG_BOOTP_BOOTFILESIZE
		CONFIG_BOOTP_DNS
		CONFIG_BOOTP_DNS2
		CONFIG_BOOTP_SEND_HOSTNAME
		CONFIG_BOOTP_NTPSERVER
		CONFIG_BOOTP_TIMEOFFSET
		CONFIG_BOOTP_VENDOREX
		CONFIG_BOOTP_MAY_FAIL

		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
		environment variable, not the BOOTP server.

		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
		after the configured retry count, the call will fail
		instead of starting over.  This can be used to fail over
		to Link-local IP address configuration if the DHCP server
		is not available.

		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
		serverip from a DHCP server, it is possible that more
		than one DNS serverip is offered to the client.
		If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS
		serverip will be stored in the additional environment
		variable "dnsip2". The first DNS serverip is always
		stored in the variable "dnsip", when CONFIG_BOOTP_DNS
		is defined.

		CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
		to do a dynamic update of a DNS server. To do this, they
		need the hostname of the DHCP requester.
		If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
		of the "hostname" environment variable is passed as
		option 12 to the DHCP server.

		CONFIG_BOOTP_DHCP_REQUEST_DELAY

		A 32bit value in microseconds for a delay between
		receiving a "DHCP Offer" and sending the "DHCP Request".
		This fixes a problem with certain DHCP servers that don't
		respond 100% of the time to a "DHCP request". E.g. On an
		AT91RM9200 processor running at 180MHz, this delay needed
		to be *at least* 15,000 usec before a Windows Server 2003
		DHCP server would reply 100% of the time. I recommend at
		least 50,000 usec to be safe. The alternative is to hope
		that one of the retries will be successful but note that
		the DHCP timeout and retry process takes a longer than
		this delay.

 - Link-local IP address negotiation:
		Negotiate with other link-local clients on the local network
		for an address that doesn't require explicit configuration.
		This is especially useful if a DHCP server cannot be guaranteed
		to exist in all environments that the device must operate.

		See doc/README.link-local for more information.

 - CDP Options:
		CONFIG_CDP_DEVICE_ID

		The device id used in CDP trigger frames.

		CONFIG_CDP_DEVICE_ID_PREFIX

		A two character string which is prefixed to the MAC address
		of the device.

		CONFIG_CDP_PORT_ID

		A printf format string which contains the ascii name of
		the port. Normally is set to "eth%d" which sets
		eth0 for the first Ethernet, eth1 for the second etc.

		CONFIG_CDP_CAPABILITIES

		A 32bit integer which indicates the device capabilities;
		0x00000010 for a normal host which does not forwards.

		CONFIG_CDP_VERSION

		An ascii string containing the version of the software.

		CONFIG_CDP_PLATFORM

		An ascii string containing the name of the platform.

		CONFIG_CDP_TRIGGER

		A 32bit integer sent on the trigger.

		CONFIG_CDP_POWER_CONSUMPTION

		A 16bit integer containing the power consumption of the
		device in .1 of milliwatts.

		CONFIG_CDP_APPLIANCE_VLAN_TYPE

		A byte containing the id of the VLAN.

- Status LED:	CONFIG_STATUS_LED

		Several configurations allow to display the current
		status using a LED. For instance, the LED will blink
		fast while running U-Boot code, stop blinking as
		soon as a reply to a BOOTP request was received, and
		start blinking slow once the Linux kernel is running
		(supported by a status LED driver in the Linux
		kernel). Defining CONFIG_STATUS_LED enables this
		feature in U-Boot.

		Additional options:

		CONFIG_GPIO_LED
		The status LED can be connected to a GPIO pin.
		In such cases, the gpio_led driver can be used as a
		status LED backend implementation. Define CONFIG_GPIO_LED
		to include the gpio_led driver in the U-Boot binary.

		CONFIG_GPIO_LED_INVERTED_TABLE
		Some GPIO connected LEDs may have inverted polarity in which
		case the GPIO high value corresponds to LED off state and
		GPIO low value corresponds to LED on state.
		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
		with a list of GPIO LEDs that have inverted polarity.

- CAN Support:	CONFIG_CAN_DRIVER

		Defining CONFIG_CAN_DRIVER enables CAN driver support
		on those systems that support this (optional)
		feature, like the TQM8xxL modules.

- I2C Support:	CONFIG_SYS_I2C

		This enable the NEW i2c subsystem, and will allow you to use
		i2c commands at the u-boot command line (as long as you set
		CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
		based realtime clock chips or other i2c devices. See
		common/cmd_i2c.c for a description of the command line
		interface.

		ported i2c driver to the new framework:
		- drivers/i2c/soft_i2c.c:
		  - activate first bus with CONFIG_SYS_I2C_SOFT define
		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
		    for defining speed and slave address
		  - activate second bus with I2C_SOFT_DECLARATIONS2 define
		    CONFIG_SYS_I2C_SOFT_SPEED_2 and CONFIG_SYS_I2C_SOFT_SLAVE_2
		    for defining speed and slave address
		  - activate third bus with I2C_SOFT_DECLARATIONS3 define
		    CONFIG_SYS_I2C_SOFT_SPEED_3 and CONFIG_SYS_I2C_SOFT_SLAVE_3
		    for defining speed and slave address
		  - activate fourth bus with I2C_SOFT_DECLARATIONS4 define
		    CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
		    for defining speed and slave address

		- drivers/i2c/fsl_i2c.c:
		  - activate i2c driver with CONFIG_SYS_I2C_FSL
		    define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
		    offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
		    CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
		    bus.
		  - If your board supports a second fsl i2c bus, define
		    CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
		    CONFIG_SYS_FSL_I2C2_SPEED for the speed and
		    CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
		    second bus.

		- drivers/i2c/tegra_i2c.c:
		  - activate this driver with CONFIG_SYS_I2C_TEGRA
		  - This driver adds 4 i2c buses with a fix speed from
		    100000 and the slave addr 0!

		- drivers/i2c/ppc4xx_i2c.c
		  - activate this driver with CONFIG_SYS_I2C_PPC4XX
		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1

		- drivers/i2c/i2c_mxc.c
		  - activate this driver with CONFIG_SYS_I2C_MXC
		  - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED
		  - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE
		  - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED
		  - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE
		  - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED
		  - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE
		If thoses defines are not set, default value is 100000
		for speed, and 0 for slave.

		- drivers/i2c/rcar_i2c.c:
		  - activate this driver with CONFIG_SYS_I2C_RCAR
		  - This driver adds 4 i2c buses

		  - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
		  - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
		  - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
		  - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
		  - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
		  - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
		  - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
		  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
		  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses

		- drivers/i2c/sh_i2c.c:
		  - activate this driver with CONFIG_SYS_I2C_SH
		  - This driver adds from 2 to 5 i2c buses

		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
		  - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
		  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
		  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses

		- drivers/i2c/omap24xx_i2c.c
		  - activate this driver with CONFIG_SYS_I2C_OMAP24XX
		  - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
		  - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
		  - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
		  - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
		  - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
		  - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
		  - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
		  - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
		  - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
		  - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4

		- drivers/i2c/zynq_i2c.c
		  - activate this driver with CONFIG_SYS_I2C_ZYNQ
		  - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
		  - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr

		- drivers/i2c/s3c24x0_i2c.c:
		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420
		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
		    with a fix speed from 100000 and the slave addr 0!

		- drivers/i2c/ihs_i2c.c
		  - activate this driver with CONFIG_SYS_I2C_IHS
		  - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
		  - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
		  - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
		  - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
		  - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
		  - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
		  - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
		  - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
		  - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3

		additional defines:

		CONFIG_SYS_NUM_I2C_BUSES
		Hold the number of i2c busses you want to use. If you
		don't use/have i2c muxes on your i2c bus, this
		is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can
		omit this define.

		CONFIG_SYS_I2C_DIRECT_BUS
		define this, if you don't use i2c muxes on your hardware.
		if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
		omit this define.

		CONFIG_SYS_I2C_MAX_HOPS
		define how many muxes are maximal consecutively connected
		on one i2c bus. If you not use i2c muxes, omit this
		define.

		CONFIG_SYS_I2C_BUSES
		hold a list of busses you want to use, only used if
		CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
		a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
		CONFIG_SYS_NUM_I2C_BUSES = 9:

		 CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP}}, \
					{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
					{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
					{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
					{0, {{I2C_MUX_PCA9547, 0x70, 4}}}, \
					{0, {{I2C_MUX_PCA9547, 0x70, 5}}}, \
					{1, {I2C_NULL_HOP}}, \
					{1, {{I2C_MUX_PCA9544, 0x72, 1}}}, \
					{1, {{I2C_MUX_PCA9544, 0x72, 2}}}, \
					}

		which defines
			bus 0 on adapter 0 without a mux
			bus 1 on adapter 0 with a PCA9547 on address 0x70 port 1
			bus 2 on adapter 0 with a PCA9547 on address 0x70 port 2
			bus 3 on adapter 0 with a PCA9547 on address 0x70 port 3
			bus 4 on adapter 0 with a PCA9547 on address 0x70 port 4
			bus 5 on adapter 0 with a PCA9547 on address 0x70 port 5
			bus 6 on adapter 1 without a mux
			bus 7 on adapter 1 with a PCA9544 on address 0x72 port 1
			bus 8 on adapter 1 with a PCA9544 on address 0x72 port 2

		If you do not have i2c muxes on your board, omit this define.

- Legacy I2C Support:	CONFIG_HARD_I2C

		NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
		provides the following compelling advantages:

		- more than one i2c adapter is usable
		- approved multibus support
		- better i2c mux support

		** Please consider updating your I2C driver now. **

		These enable legacy I2C serial bus commands. Defining
		CONFIG_HARD_I2C will include the appropriate I2C driver
		for the selected CPU.

		This will allow you to use i2c commands at the u-boot
		command line (as long as you set CONFIG_CMD_I2C in
		CONFIG_COMMANDS) and communicate with i2c based realtime
		clock chips. See common/cmd_i2c.c for a description of the
		command line interface.

		CONFIG_HARD_I2C selects a hardware I2C controller.

		There are several other quantities that must also be
		defined when you define CONFIG_HARD_I2C.

		In both cases you will need to define CONFIG_SYS_I2C_SPEED
		to be the frequency (in Hz) at which you wish your i2c bus
		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
		the CPU's i2c node address).

		Now, the u-boot i2c code for the mpc8xx
		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
		and so its address should therefore be cleared to 0 (See,
		eg, MPC823e User's Manual p.16-473). So, set
		CONFIG_SYS_I2C_SLAVE to 0.

		CONFIG_SYS_I2C_INIT_MPC5XXX

		When a board is reset during an i2c bus transfer
		chips might think that the current transfer is still
		in progress.  Reset the slave devices by sending start
		commands until the slave device responds.

		That's all that's required for CONFIG_HARD_I2C.

		If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
		then the following macros need to be defined (examples are
		from include/configs/lwmon.h):

		I2C_INIT

		(Optional). Any commands necessary to enable the I2C
		controller or configure ports.

		eg: #define I2C_INIT (immr->im_cpm.cp_pbdir |=	PB_SCL)

		I2C_PORT

		(Only for MPC8260 CPU). The I/O port to use (the code
		assumes both bits are on the same port). Valid values
		are 0..3 for ports A..D.

		I2C_ACTIVE

		The code necessary to make the I2C data line active
		(driven).  If the data line is open collector, this
		define can be null.

		eg: #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |=  PB_SDA)

		I2C_TRISTATE

		The code necessary to make the I2C data line tri-stated
		(inactive).  If the data line is open collector, this
		define can be null.

		eg: #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)

		I2C_READ

		Code that returns true if the I2C data line is high,
		false if it is low.

		eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)

		I2C_SDA(bit)

		If <bit> is true, sets the I2C data line high. If it
		is false, it clears it (low).

		eg: #define I2C_SDA(bit) \
			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA

		I2C_SCL(bit)

		If <bit> is true, sets the I2C clock line high. If it
		is false, it clears it (low).

		eg: #define I2C_SCL(bit) \
			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL

		I2C_DELAY

		This delay is invoked four times per clock cycle so this
		controls the rate of data transfer.  The data rate thus
		is 1 / (I2C_DELAY * 4). Often defined to be something
		like:

		#define I2C_DELAY  udelay(2)

		CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA

		If your arch supports the generic GPIO framework (asm/gpio.h),
		then you may alternatively define the two GPIOs that are to be
		used as SCL / SDA.  Any of the previous I2C_xxx macros will
		have GPIO-based defaults assigned to them as appropriate.

		You should define these to the GPIO value as given directly to
		the generic GPIO functions.

		CONFIG_SYS_I2C_INIT_BOARD

		When a board is reset during an i2c bus transfer
		chips might think that the current transfer is still
		in progress. On some boards it is possible to access
		the i2c SCLK line directly, either by using the
		processor pin as a GPIO or by having a second pin
		connected to the bus. If this option is defined a
		custom i2c_init_board() routine in boards/xxx/board.c
		is run early in the boot sequence.

		CONFIG_SYS_I2C_BOARD_LATE_INIT

		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
		defined a custom i2c_board_late_init() routine in
		boards/xxx/board.c is run AFTER the operations in i2c_init()
		is completed. This callpoint can be used to unreset i2c bus
		using CPU i2c controller register accesses for CPUs whose i2c
		controller provide such a method. It is called at the end of
		i2c_init() to allow i2c_init operations to setup the i2c bus
		controller on the CPU (e.g. setting bus speed & slave address).

		CONFIG_I2CFAST (PPC405GP|PPC405EP only)

		This option enables configuration of bi_iic_fast[] flags
		in u-boot bd_info structure based on u-boot environment
		variable "i2cfast". (see also i2cfast)

		CONFIG_I2C_MULTI_BUS

		This option allows the use of multiple I2C buses, each of which
		must have a controller.	 At any point in time, only one bus is
		active.	 To switch to a different bus, use the 'i2c dev' command.
		Note that bus numbering is zero-based.

		CONFIG_SYS_I2C_NOPROBES

		This option specifies a list of I2C devices that will be skipped
		when the 'i2c probe' command is issued.	 If CONFIG_I2C_MULTI_BUS
		is set, specify a list of bus-device pairs.  Otherwise, specify
		a 1D array of device addresses

		e.g.
			#undef	CONFIG_I2C_MULTI_BUS
			#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}

		will skip addresses 0x50 and 0x68 on a board with one I2C bus

			#define CONFIG_I2C_MULTI_BUS
			#define CONFIG_SYS_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}

		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1

		CONFIG_SYS_SPD_BUS_NUM

		If defined, then this indicates the I2C bus number for DDR SPD.
		If not defined, then U-Boot assumes that SPD is on I2C bus 0.

		CONFIG_SYS_RTC_BUS_NUM

		If defined, then this indicates the I2C bus number for the RTC.
		If not defined, then U-Boot assumes that RTC is on I2C bus 0.

		CONFIG_SYS_DTT_BUS_NUM

		If defined, then this indicates the I2C bus number for the DTT.
		If not defined, then U-Boot assumes that DTT is on I2C bus 0.

		CONFIG_SYS_I2C_DTT_ADDR:

		If defined, specifies the I2C address of the DTT device.
		If not defined, then U-Boot uses predefined value for
		specified DTT device.

		CONFIG_SOFT_I2C_READ_REPEATED_START

		defining this will force the i2c_read() function in
		the soft_i2c driver to perform an I2C repeated start
		between writing the address pointer and reading the
		data.  If this define is omitted the default behaviour
		of doing a stop-start sequence will be used.  Most I2C
		devices can use either method, but some require one or
		the other.

- SPI Support:	CONFIG_SPI

		Enables SPI driver (so far only tested with
		SPI EEPROM, also an instance works with Crystal A/D and
		D/As on the SACSng board)

		CONFIG_SH_SPI

		Enables the driver for SPI controller on SuperH. Currently
		only SH7757 is supported.

		CONFIG_SPI_X

		Enables extended (16-bit) SPI EEPROM addressing.
		(symmetrical to CONFIG_I2C_X)

		CONFIG_SOFT_SPI

		Enables a software (bit-bang) SPI driver rather than
		using hardware support. This is a general purpose
		driver that only requires three general I/O port pins
		(two outputs, one input) to function. If this is
		defined, the board configuration must define several
		SPI configuration items (port pins to use, etc). For
		an example, see include/configs/sacsng.h.

		CONFIG_HARD_SPI

		Enables a hardware SPI driver for general-purpose reads
		and writes.  As with CONFIG_SOFT_SPI, the board configuration
		must define a list of chip-select function pointers.
		Currently supported on some MPC8xxx processors.	 For an
		example, see include/configs/mpc8349emds.h.

		CONFIG_MXC_SPI

		Enables the driver for the SPI controllers on i.MX and MXC
		SoCs. Currently i.MX31/35/51 are supported.

		CONFIG_SYS_SPI_MXC_WAIT
		Timeout for waiting until spi transfer completed.
		default: (CONFIG_SYS_HZ/100)     /* 10 ms */

- FPGA Support: CONFIG_FPGA

		Enables FPGA subsystem.

		CONFIG_FPGA_<vendor>

		Enables support for specific chip vendors.
		(ALTERA, XILINX)

		CONFIG_FPGA_<family>

		Enables support for FPGA family.
		(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)

		CONFIG_FPGA_COUNT

		Specify the number of FPGA devices to support.

		CONFIG_CMD_FPGA_LOADMK

		Enable support for fpga loadmk command

		CONFIG_CMD_FPGA_LOADP

		Enable support for fpga loadp command - load partial bitstream

		CONFIG_CMD_FPGA_LOADBP

		Enable support for fpga loadbp command - load partial bitstream
		(Xilinx only)

		CONFIG_SYS_FPGA_PROG_FEEDBACK

		Enable printing of hash marks during FPGA configuration.

		CONFIG_SYS_FPGA_CHECK_BUSY

		Enable checks on FPGA configuration interface busy
		status by the configuration function. This option
		will require a board or device specific function to
		be written.

		CONFIG_FPGA_DELAY

		If defined, a function that provides delays in the FPGA
		configuration driver.

		CONFIG_SYS_FPGA_CHECK_CTRLC
		Allow Control-C to interrupt FPGA configuration

		CONFIG_SYS_FPGA_CHECK_ERROR

		Check for configuration errors during FPGA bitfile
		loading. For example, abort during Virtex II
		configuration if the INIT_B line goes low (which
		indicated a CRC error).

		CONFIG_SYS_FPGA_WAIT_INIT

		Maximum time to wait for the INIT_B line to deassert
		after PROB_B has been deasserted during a Virtex II
		FPGA configuration sequence. The default time is 500
		ms.

		CONFIG_SYS_FPGA_WAIT_BUSY

		Maximum time to wait for BUSY to deassert during
		Virtex II FPGA configuration. The default is 5 ms.

		CONFIG_SYS_FPGA_WAIT_CONFIG

		Time to wait after FPGA configuration. The default is
		200 ms.

- Configuration Management:
		CONFIG_IDENT_STRING

		If defined, this string will be added to the U-Boot
		version information (U_BOOT_VERSION)

- Vendor Parameter Protection:

		U-Boot considers the values of the environment
		variables "serial#" (Board Serial Number) and
		"ethaddr" (Ethernet Address) to be parameters that
		are set once by the board vendor / manufacturer, and
		protects these variables from casual modification by
		the user. Once set, these variables are read-only,
		and write or delete attempts are rejected. You can
		change this behaviour:

		If CONFIG_ENV_OVERWRITE is #defined in your config
		file, the write protection for vendor parameters is
		completely disabled. Anybody can change or delete
		these parameters.

		Alternatively, if you #define _both_ CONFIG_ETHADDR
		_and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default
		Ethernet address is installed in the environment,
		which can be changed exactly ONCE by the user. [The
		serial# is unaffected by this, i. e. it remains
		read-only.]

		The same can be accomplished in a more flexible way
		for any variable by configuring the type of access
		to allow for those variables in the ".flags" variable
		or define CONFIG_ENV_FLAGS_LIST_STATIC.

- Protected RAM:
		CONFIG_PRAM

		Define this variable to enable the reservation of
		"protected RAM", i. e. RAM which is not overwritten
		by U-Boot. Define CONFIG_PRAM to hold the number of
		kB you want to reserve for pRAM. You can overwrite
		this default value by defining an environment
		variable "pram" to the number of kB you want to
		reserve. Note that the board info structure will
		still show the full amount of RAM. If pRAM is
		reserved, a new environment variable "mem" will
		automatically be defined to hold the amount of
		remaining RAM in a form that can be passed as boot
		argument to Linux, for instance like that:

			setenv bootargs ... mem=\${mem}
			saveenv

		This way you can tell Linux not to use this memory,
		either, which results in a memory region that will
		not be affected by reboots.

		*WARNING* If your board configuration uses automatic
		detection of the RAM size, you must make sure that
		this memory test is non-destructive. So far, the
		following board configurations are known to be
		"pRAM-clean":

			IVMS8, IVML24, SPD8xx, TQM8xxL,
			HERMES, IP860, RPXlite, LWMON,
			FLAGADM, TQM8260

- Access to physical memory region (> 4GB)
		Some basic support is provided for operations on memory not
		normally accessible to U-Boot - e.g. some architectures
		support access to more than 4GB of memory on 32-bit
		machines using physical address extension or similar.
		Define CONFIG_PHYSMEM to access this basic support, which
		currently only supports clearing the memory.

- Error Recovery:
		CONFIG_PANIC_HANG

		Define this variable to stop the system in case of a
		fatal error, so that you have to reset it manually.
		This is probably NOT a good idea for an embedded
		system where you want the system to reboot
		automatically as fast as possible, but it may be
		useful during development since you can try to debug
		the conditions that lead to the situation.

		CONFIG_NET_RETRY_COUNT

		This variable defines the number of retries for
		network operations like ARP, RARP, TFTP, or BOOTP
		before giving up the operation. If not defined, a
		default value of 5 is used.

		CONFIG_ARP_TIMEOUT

		Timeout waiting for an ARP reply in milliseconds.

		CONFIG_NFS_TIMEOUT

		Timeout in milliseconds used in NFS protocol.
		If you encounter "ERROR: Cannot umount" in nfs command,
		try longer timeout such as
		#define CONFIG_NFS_TIMEOUT 10000UL

- Command Interpreter:
		CONFIG_AUTO_COMPLETE

		Enable auto completion of commands using TAB.

		Note that this feature has NOT been implemented yet
		for the "hush" shell.


		CONFIG_SYS_HUSH_PARSER

		Define this variable to enable the "hush" shell (from
		Busybox) as command line interpreter, thus enabling
		powerful command line syntax like
		if...then...else...fi conditionals or `&&' and '||'
		constructs ("shell scripts").

		If undefined, you get the old, much simpler behaviour
		with a somewhat smaller memory footprint.


		CONFIG_SYS_PROMPT_HUSH_PS2

		This defines the secondary prompt string, which is
		printed when the command interpreter needs more input
		to complete a command. Usually "> ".

	Note:

		In the current implementation, the local variables
		space and global environment variables space are
		separated. Local variables are those you define by
		simply typing `name=value'. To access a local
		variable later on, you have write `$name' or
		`${name}'; to execute the contents of a variable
		directly type `$name' at the command prompt.

		Global environment variables are those you use
		setenv/printenv to work with. To run a command stored
		in such a variable, you need to use the run command,
		and you must not use the '$' sign to access them.

		To store commands and special characters in a
		variable, please use double quotation marks
		surrounding the whole text of the variable, instead
		of the backslashes before semicolons and special
		symbols.

- Commandline Editing and History:
		CONFIG_CMDLINE_EDITING

		Enable editing and History functions for interactive
		commandline input operations

- Default Environment:
		CONFIG_EXTRA_ENV_SETTINGS

		Define this to contain any number of null terminated
		strings (variable = value pairs) that will be part of
		the default environment compiled into the boot image.

		For example, place something like this in your
		board's config file:

		#define CONFIG_EXTRA_ENV_SETTINGS \
			"myvar1=value1\0" \
			"myvar2=value2\0"

		Warning: This method is based on knowledge about the
		internal format how the environment is stored by the
		U-Boot code. This is NOT an official, exported
		interface! Although it is unlikely that this format
		will change soon, there is no guarantee either.
		You better know what you are doing here.

		Note: overly (ab)use of the default environment is
		discouraged. Make sure to check other ways to preset
		the environment like the "source" command or the
		boot command first.

		CONFIG_ENV_VARS_UBOOT_CONFIG

		Define this in order to add variables describing the
		U-Boot build configuration to the default environment.
		These will be named arch, cpu, board, vendor, and soc.

		Enabling this option will cause the following to be defined:

		- CONFIG_SYS_ARCH
		- CONFIG_SYS_CPU
		- CONFIG_SYS_BOARD
		- CONFIG_SYS_VENDOR
		- CONFIG_SYS_SOC

		CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

		Define this in order to add variables describing certain
		run-time determined information about the hardware to the
		environment.  These will be named board_name, board_rev.

		CONFIG_DELAY_ENVIRONMENT

		Normally the environment is loaded when the board is
		intialised so that it is available to U-Boot. This inhibits
		that so that the environment is not available until
		explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
		this is instead controlled by the value of
		/config/load-environment.

- DataFlash Support:
		CONFIG_HAS_DATAFLASH

		Defining this option enables DataFlash features and
		allows to read/write in Dataflash via the standard
		commands cp, md...

- Serial Flash support
		CONFIG_CMD_SF

		Defining this option enables SPI flash commands
		'sf probe/read/write/erase/update'.

		Usage requires an initial 'probe' to define the serial
		flash parameters, followed by read/write/erase/update
		commands.

		The following defaults may be provided by the platform
		to handle the common case when only a single serial
		flash is present on the system.

		CONFIG_SF_DEFAULT_BUS		Bus identifier
		CONFIG_SF_DEFAULT_CS		Chip-select
		CONFIG_SF_DEFAULT_MODE 		(see include/spi.h)
		CONFIG_SF_DEFAULT_SPEED		in Hz

		CONFIG_CMD_SF_TEST

		Define this option to include a destructive SPI flash
		test ('sf test').

		CONFIG_SPI_FLASH_BAR		Ban/Extended Addr Reg

		Define this option to use the Bank addr/Extended addr
		support on SPI flashes which has size > 16Mbytes.

		CONFIG_SF_DUAL_FLASH		Dual flash memories

		Define this option to use dual flash support where two flash
		memories can be connected with a given cs line.
		currently Xilinx Zynq qspi support these type of connections.

		CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
		enable the W#/Vpp signal to disable writing to the status
		register on ST MICRON flashes like the N25Q128.
		The status register write enable/disable bit, combined with
		the W#/VPP signal provides hardware data protection for the
		device as follows: When the enable/disable bit is set to 1,
		and the W#/VPP signal is driven LOW, the status register
		nonvolatile bits become read-only and the WRITE STATUS REGISTER
		operation will not execute. The only way to exit this
		hardware-protected mode is to drive W#/VPP HIGH.

- SystemACE Support:
		CONFIG_SYSTEMACE

		Adding this option adds support for Xilinx SystemACE
		chips attached via some sort of local bus. The address
		of the chip must also be defined in the
		CONFIG_SYS_SYSTEMACE_BASE macro. For example:

		#define CONFIG_SYSTEMACE
		#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000

		When SystemACE support is added, the "ace" device type
		becomes available to the fat commands, i.e. fatls.

- TFTP Fixed UDP Port:
		CONFIG_TFTP_PORT

		If this is defined, the environment variable tftpsrcp
		is used to supply the TFTP UDP source port value.
		If tftpsrcp isn't defined, the normal pseudo-random port
		number generator is used.

		Also, the environment variable tftpdstp is used to supply
		the TFTP UDP destination port value.  If tftpdstp isn't
		defined, the normal port 69 is used.

		The purpose for tftpsrcp is to allow a TFTP server to
		blindly start the TFTP transfer using the pre-configured
		target IP address and UDP port. This has the effect of
		"punching through" the (Windows XP) firewall, allowing
		the remainder of the TFTP transfer to proceed normally.
		A better solution is to properly configure the firewall,
		but sometimes that is not allowed.