On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>