Skip to content
Snippets Groups Projects
Commit 3d078ce6 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Coding style cleanup

parent 6bdf4306
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 273 additions and 344 deletions
CHANGELOG
+ 2
− 0
View file @ 3d078ce6
......@@ -2,6 +2,8 @@
Changes for U-Boot 1.1.4:
======================================================================
* Coding style cleanup
* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
......
MAINTAINERS
+ 2
− 2
View file @ 3d078ce6
......@@ -278,8 +278,8 @@ Yusdi Santoso <yusdi_santoso@adaptec.com>
Travis Sawyer (travis.sawyer@sandburst.com>
KAREF PPC440GX
METROBOX PPC440GX
KAREF PPC440GX
METROBOX PPC440GX
XPEDITE1K PPC440GX
Peter De Schrijver <p2@mind.be>
......
MAKEALL
+ 9
− 9
View file @ 3d078ce6
......@@ -60,17 +60,17 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
ADCIOP AR405 ASH405 bubinga \
ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \
ebony ERIC EXBITGEN HUB405 \
JSE KAREF METROBOX MIP405 \
MIP405T ML2 ml300 ocotea \
OCRTC ORSG PCI405 PIP405 \
PLU405 PMC405 PPChameleonEVB VOH405 \
W7OLMC W7OLMG walnut WUH405 \
XPEDITE1K yellowstone yosemite \
JSE KAREF METROBOX MIP405 \
MIP405T ML2 ml300 ocotea \
OCRTC ORSG PCI405 PIP405 \
PLU405 PMC405 PPChameleonEVB VOH405 \
W7OLMC W7OLMG walnut WUH405 \
XPEDITE1K yellowstone yosemite \
"
#########################################################################
......@@ -90,7 +90,7 @@ LIST_824x=" \
debris eXalion HIDDEN_DRAGON MOUSSE \
MUSENKI MVBLUE OXC PN62 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
sbc8240 \
sbc8240 \
"
#########################################################################
......@@ -164,7 +164,7 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
#########################################################################
LIST_ARM9=" \
at91rm9200dk cmc_pu2 integratorcp integratorap \
at91rm9200dk cmc_pu2 integratorcp integratorap \
lpd7a400 mx1ads mx1fs2 omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
......
board/sandburst/common/ppc440gx_i2c.c
+ 1
− 4
View file @ 3d078ce6
......@@ -39,8 +39,6 @@
#ifdef CONFIG_I2C_BUS1
#define IIC_OK 0
#define IIC_NOK 1
#define IIC_NOK_LA 2 /* Lost arbitration */
......@@ -511,5 +509,4 @@ U_BOOT_CMD(
"\n -discover valid I2C chip addresses\n"
);
#endif
#endif /* CONFIG_I2C_BUS1 */
board/sandburst/common/ppc440gx_i2c.h
+ 1
− 4
View file @ 3d078ce6
......@@ -34,11 +34,8 @@
#endif
#include <i2c.h>
#ifdef CONFIG_HARD_I2C
#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
......@@ -64,4 +61,4 @@ int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
#endif
#endif /* CONFIG_HARD_I2C */
board/sandburst/common/sb_common.c
+ 18
− 18
View file @ 3d078ce6
......@@ -34,7 +34,7 @@ long int fixed_sdram (void);
/*************************************************************************
* metrobox_get_master
*
* PRI_N - active low signal. If the GPIO pin is low we are the master
* PRI_N - active low signal. If the GPIO pin is low we are the master
*
************************************************************************/
int sbcommon_get_master(void)
......@@ -81,7 +81,7 @@ unsigned short sbcommon_get_serial_number(void)
unsigned short sernum;
/* Get the board serial number from eeprom */
/* Initialize I2C */
/* Initialize I2C */
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
......@@ -96,7 +96,7 @@ unsigned short sbcommon_get_serial_number(void)
/*************************************************************************
* sbcommon_fans
*
* Spin up fans 2 & 3 to get some air moving. OS will take care
* Spin up fans 2 & 3 to get some air moving. OS will take care
* of the rest. This is mostly a precaution...
*
* Assumes i2c bus 1 is ready.
......@@ -253,8 +253,8 @@ int testdram (void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
*
* Assumes: 128 MB, non-ECC, non-registered
* PLB @ 133 MHz
* Assumes: 128 MB, non-ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
long int fixed_sdram (void)
......@@ -264,11 +264,11 @@ long int fixed_sdram (void)
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
......@@ -276,25 +276,25 @@ long int fixed_sdram (void)
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) {
mfsdram (mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
return (128 * 1024 * 1024); /* 128 MB */
return (128 * 1024 * 1024); /* 128 MB */
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
......
board/sandburst/common/sb_common.h
+ 19
− 26
View file @ 3d078ce6
......@@ -30,38 +30,35 @@
#include <i2c.h>
#include "ppc440gx_i2c.h"
/*
* GPIO Settings
*/
/* Chassis settings */
#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */
#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */
/* Debug LEDs */
#define SBCOMMON_GPIO_DBGLED_0 0x00000400
#define SBCOMMON_GPIO_DBGLED_1 0x00000200
#define SBCOMMON_GPIO_DBGLED_2 0x00100000
#define SBCOMMON_GPIO_DBGLED_3 0x00000100
#define SBCOMMON_GPIO_DBGLED_0 0x00000400
#define SBCOMMON_GPIO_DBGLED_1 0x00000200
#define SBCOMMON_GPIO_DBGLED_2 0x00100000
#define SBCOMMON_GPIO_DBGLED_3 0x00000100
#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3)
#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3)
#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
#define SBCOMMON_GPIO_SYS_FAULT 0x00000080
#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040
#define SBCOMMON_GPIO_SYS_STATUS 0x00000020
#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS)
#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3 | \
SBCOMMON_GPIO_SYS_STATUS)
#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \
SBCOMMON_GPIO_DBGLED_1 | \
SBCOMMON_GPIO_DBGLED_2 | \
SBCOMMON_GPIO_DBGLED_3 | \
SBCOMMON_GPIO_SYS_STATUS)
typedef struct ppc440_gpio_regs {
volatile unsigned long out;
......@@ -71,13 +68,9 @@ typedef struct ppc440_gpio_regs {
volatile unsigned long in;
} __attribute__((packed)) ppc440_gpio_regs_t;
int sbcommon_get_master(void);
int sbcommon_secondary_present(void);
unsigned short sbcommon_get_serial_number(void);
void sbcommon_fans(void);
#endif /* __SBCOMMON_H__ */
board/sandburst/karef/karef.c
+ 1
− 31
View file @ 3d078ce6
......@@ -33,8 +33,6 @@
#include "../common/sb_common.h"
#include "../common/ppc440gx_i2c.h"
void fpga_init (void);
KAREF_BOARD_ID_ST board_id_as[] =
......@@ -53,13 +51,11 @@ KAREF_BOARD_ID_ST ofem_board_id_as[] =
{"Reserved"},
};
/*************************************************************************
* board_early_init_f
*
* Setup chip selects, initialize the Opto-FPGA, initialize
* interrupt polarity and triggers.
*
************************************************************************/
int board_early_init_f (void)
{
......@@ -196,7 +192,6 @@ int board_early_init_f (void)
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
......@@ -241,7 +236,6 @@ int board_early_init_f (void)
* checkboard
*
* Dump pertinent info to the console
*
************************************************************************/
int checkboard (void)
{
......@@ -326,12 +320,10 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* misc_init_f
*
* Initialize I2C bus one to gain access to the fans
*
************************************************************************/
int misc_init_f (void)
{
......@@ -345,11 +337,11 @@ int misc_init_f (void)
return (0);
}
/*************************************************************************
* misc_init_r
*
* Do nothing.
*
************************************************************************/
int misc_init_r (void)
{
......@@ -409,20 +401,11 @@ int misc_init_r (void)
printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
}
return (0);
}
/*************************************************************************
* ide_set_reset
*
*
*
************************************************************************/
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
......@@ -441,9 +424,6 @@ void ide_set_reset(int on)
/*************************************************************************
* fpga_init
*
*
*
************************************************************************/
void fpga_init(void)
{
......@@ -498,8 +478,6 @@ void fpga_init(void)
return;
}
int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned short sernum;
......@@ -560,7 +538,6 @@ int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return(1);
}
int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned short sernum;
......@@ -593,15 +570,8 @@ int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return(1);
}
U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
"kasetup - Set environment to factory defaults\n", NULL);
U_BOOT_CMD(karecover, 1, 1, karefRecover,
"karecover - Set environment to allow for fs recovery\n", NULL);
board/sandburst/metrobox/metrobox.c
+ 1
− 28
View file @ 3d078ce6
......@@ -32,8 +32,6 @@
#include "../common/ppc440gx_i2c.h"
#include "../common/sb_common.h"
void fpga_init (void);
METROBOX_BOARD_ID_ST board_id_as[] =
......@@ -43,13 +41,11 @@ METROBOX_BOARD_ID_ST board_id_as[] =
{"Reserved"}, /* Reserved for future use */
};
/*************************************************************************
* board_early_init_f
*
* Setup chip selects, initialize the Opto-FPGA, initialize
* interrupt polarity and triggers.
*
************************************************************************/
int board_early_init_f (void)
{
......@@ -186,7 +182,6 @@ int board_early_init_f (void)
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
+-------------------------------------------------------------------*/
......@@ -226,12 +221,10 @@ int board_early_init_f (void)
return 0;
}
/*************************************************************************
* checkboard
*
* Dump pertinent info to the console
*
************************************************************************/
int checkboard (void)
{
......@@ -295,12 +288,10 @@ int checkboard (void)
return (0);
}
/*************************************************************************
* misc_init_f
*
* Initialize I2C bus one to gain access to the fans
*
************************************************************************/
int misc_init_f (void)
{
......@@ -314,11 +305,11 @@ int misc_init_f (void)
return (0);
}
/*************************************************************************
* misc_init_r
*
* Do nothing.
*
************************************************************************/
int misc_init_r (void)
{
......@@ -384,13 +375,8 @@ int misc_init_r (void)
return (0);
}
/*************************************************************************
* ide_set_reset
*
*
*
************************************************************************/
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
......@@ -408,9 +394,6 @@ void ide_set_reset(int on)
/*************************************************************************
* fpga_init
*
*
*
************************************************************************/
void fpga_init(void)
{
......@@ -462,8 +445,6 @@ void fpga_init(void)
return;
}
int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned short sernum;
......@@ -524,7 +505,6 @@ int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return(1);
}
int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned short sernum;
......@@ -556,15 +536,8 @@ int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return(1);
}
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
"mbsetup - Set environment to factory defaults\n", NULL);
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
"mbrecover - Set environment to allow for fs recovery\n", NULL);
board/sandburst/metrobox/metrobox.h
+ 11
− 14
View file @ 3d078ce6
......@@ -30,19 +30,16 @@ typedef struct metrobox_board_id_s {
/* Metrobox Opto-FPGA registers and definitions */
#include "hal_xc_auto.h"
typedef struct opto_fpga_regs_s
{
volatile unsigned long revision_ul; /* Read Only */
volatile unsigned long reset_ul; /* Read/Write */
volatile unsigned long status_ul; /* Read Only */
volatile unsigned long interrupt_ul; /* Read Only */
volatile unsigned long mask_ul; /* Read/Write */
volatile unsigned long scratch_ul; /* Read/Write */
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long boardinfo_ul; /* Read Only */
} OPTO_FPGA_REGS_ST __attribute__((packed)), *OPTO_FPGA_REGS_PST;
typedef struct opto_fpga_regs_s {
volatile unsigned long revision_ul; /* Read Only */
volatile unsigned long reset_ul; /* Read/Write */
volatile unsigned long status_ul; /* Read Only */
volatile unsigned long interrupt_ul; /* Read Only */
volatile unsigned long mask_ul; /* Read/Write */
volatile unsigned long scratch_ul; /* Read/Write */
volatile unsigned long scrmask_ul; /* Read/Write */
volatile unsigned long control_ul; /* Read/Write */
volatile unsigned long boardinfo_ul; /* Read Only */
} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST;
#endif /* __METROBOX_H__ */
include/configs/KAREF.h
+ 100
− 100
View file @ 3d078ce6
......@@ -22,7 +22,7 @@
/************************************************************************
* KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
* design.
* design.
***********************************************************************/
/*
......@@ -36,14 +36,14 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
#undef CFG_DRAM_TEST /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_VERSION_VARIABLE
......@@ -54,13 +54,13 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
......@@ -69,23 +69,23 @@
#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
/* Here for completeness */
#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
/*-----------------------------------------------------------------------
* Serial Port
......@@ -108,91 +108,91 @@
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
/*-----------------------------------------------------------------------
* Console/Commands/Parser
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_PING | \
CFG_CMD_DIAG | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_ELF | \
CFG_CMD_IDE | \
CFG_CMD_FAT)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_PING | \
CFG_CMD_DIAG | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_ELF | \
CFG_CMD_IDE | \
CFG_CMD_FAT)
/* Include NetConsole support */
#define CONFIG_NETCONSOLE
......@@ -200,16 +200,16 @@
/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
#define CFG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
#define CFG_ALT_MEMTEST 1 /* use real memory test */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
#define CFG_PROMPT_HUSH_PS2 "> "
......@@ -217,20 +217,20 @@
* Console Buffer
*----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of cmd args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of cmd args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
/*-----------------------------------------------------------------------
* Memory Test
*----------------------------------------------------------------------*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*-----------------------------------------------------------------------
* Compact Flash (in true IDE mode)
......@@ -238,7 +238,7 @@
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
......@@ -248,25 +248,25 @@
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
to get to the correct offset */
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
to get to the correct offset */
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
/*-----------------------------------------------------------------------
* PCI
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
......@@ -277,10 +277,10 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
/*
......@@ -288,22 +288,22 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
#define CFG_EXTBDINFO 1 /* use extended board_info */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
#define CFG_EXTBDINFO 1 /* use extended board_info */
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
#endif /* __CONFIG_H */
include/configs/METROBOX.h
+ 108
− 108
View file @ 3d078ce6
......@@ -65,32 +65,32 @@
* Revision 1.10 2004/06/29 19:08:55 tsawyer
* Add CONFIG_MISC_INIT_R
*
* Revision 1.9 2004/06/28 21:30:53 tsawyer
* Revision 1.9 2004/06/28 21:30:53 tsawyer
* Fix default BOOTARGS
*
* Revision 1.8 2004/06/17 15:51:08 tsawyer
* Revision 1.8 2004/06/17 15:51:08 tsawyer
* auto complete
*
* Revision 1.7 2004/06/17 15:08:49 tsawyer
* Revision 1.7 2004/06/17 15:08:49 tsawyer
* Add autocomplete
*
* Revision 1.6 2004/06/15 12:33:57 tsawyer
* Revision 1.6 2004/06/15 12:33:57 tsawyer
* debugging checkpoint
*
* Revision 1.5 2004/06/12 19:48:28 tsawyer
* Revision 1.5 2004/06/12 19:48:28 tsawyer
* Debugging checkpoint
*
* Revision 1.4 2004/06/02 13:03:06 tsawyer
* Revision 1.4 2004/06/02 13:03:06 tsawyer
* Fix eth addrs
*
* Revision 1.3 2004/05/18 19:56:10 tsawyer
* Revision 1.3 2004/05/18 19:56:10 tsawyer
* Change default bootcommand to pImage.metrobox
*
* Revision 1.2 2004/05/18 14:13:44 tsawyer
* Revision 1.2 2004/05/18 14:13:44 tsawyer
* Add bringup values for bootargs and bootcommand.
* Remove definition of ipaddress and serverip addresses.
*
* Revision 1.1 2004/04/16 15:08:54 tsawyer
* Revision 1.1 2004/04/16 15:08:54 tsawyer
* Initial Revision
*
*
......@@ -102,14 +102,14 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
#undef CFG_DRAM_TEST /* Disable-takes long time!*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_VERSION_VARIABLE
......@@ -120,13 +120,13 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
......@@ -138,16 +138,16 @@
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
/*-----------------------------------------------------------------------
* Serial Port
......@@ -170,96 +170,96 @@
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
#define CONFIG_HARD_I2C 1 /* I2C hardware support */
#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
#define CONFIG_BOOTCOMMAND "tftp 8000000 pImage.metrobox;bootm 8000000"
#define CONFIG_BOOTDELAY 5 /* disable autoboot */
#define CONFIG_BOOTDELAY 5 /* disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
/*-----------------------------------------------------------------------
* Console/Commands/Parser
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_PING | \
CFG_CMD_DIAG | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_ELF | \
CFG_CMD_IDE | \
CFG_CMD_FAT)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_I2C | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_BEDBUG | \
CFG_CMD_PING | \
CFG_CMD_DIAG | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_ELF | \
CFG_CMD_IDE | \
CFG_CMD_FAT)
/* tbs 09-March-2005 Removed to be able to use 2nd serial */
/* CFG_CMD_KGDB | \ */
/* CFG_CMD_KGDB | \ */
/* Include NetConsole support */
......@@ -268,16 +268,16 @@
/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
#define CFG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
#define CFG_ALT_MEMTEST 1 /* use real memory test */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
#define CFG_PROMPT_HUSH_PS2 "> "
......@@ -285,20 +285,20 @@
* Console Buffer
*----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of cmd args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of cmd args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
/*-----------------------------------------------------------------------
* Memory Test
*----------------------------------------------------------------------*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*-----------------------------------------------------------------------
* Compact Flash (in true IDE mode)
......@@ -306,7 +306,7 @@
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
......@@ -316,25 +316,25 @@
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
to get to the correct offset */
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
to get to the correct offset */
#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
/*-----------------------------------------------------------------------
* PCI
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
......@@ -345,10 +345,10 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
/*
......@@ -356,22 +356,22 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
#endif
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
#define CFG_EXTBDINFO 1 /* use extended board_info */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_LOAD_ADDR 0x8000000 /* default load address */
#define CFG_EXTBDINFO 1 /* use extended board_info */
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
#define CFG_HZ 100 /* decr freq: 1 ms ticks */
#endif /* __CONFIG_H */
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment