Add missing Blackfin files.

blackfin_config.mk

+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__

board/ezkit533/Makefile

+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ezkit533.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/ezkit533/config.mk

+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+

board/ezkit533/ezkit533.c

+/*
+ * U-boot - ezkit533.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_MISC_INIT_R)
+#include "psd4256.h"
+#endif
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf("Board: ADI BF533 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	printf("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	int brate;
+	char *tmp = getenv("baudrate");
+	brate = simple_strtoul(tmp, NULL, 16);
+	printf("Serial Port initialized with Baud rate = %x\n",brate);
+	printf("SDRAM attributes:\n");
+	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+	       3, 3, 6, 2, 3);
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* Set direction bits for Video en/decoder reset as output	*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Deactivate Video en/decoder reset lines			*/
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+}
+#endif

board/ezkit533/flash-defines.h

+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
+#define TRUE			0x1
+#define FALSE			0x0
+#define BUFFER_SIZE		0x80000
+#define NO_COMMAND		0
+#define GET_CODES		1
+#define RESET			2
+#define WRITE			3
+#define FILL			4
+#define ERASE_ALL		5
+#define ERASE_SECT		6
+#define READ			7
+#define GET_SECTNUM		8
+#define FLASH_START_L 		0x0000
+#define FLASH_START_H 		0x2000
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE 		0x220000
+#define FLASH_MAN_ST 		2
+#define CFG_FLASH0_BASE		0x20000000
+#define RESET_VAL		0xF0
+
+
+asm("#define FLASH_START_L 0x0000");
+asm("#define FLASH_START_H 0x2000");
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int,unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, long lStride, int *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+#define WRITESEQ1		0x0AAA
+#define WRITESEQ2		0x0554
+#define WRITESEQ3		0x0AAA
+#define WRITESEQ4		0x0AAA
+#define WRITESEQ5		0x0554
+#define WRITESEQ6		0x0AAA
+#define WRITEDATA1		0xaa
+#define WRITEDATA2		0x55
+#define WRITEDATA3		0x80
+#define WRITEDATA4		0xaa
+#define WRITEDATA5		0x55
+#define WRITEDATA6		0x10
+#define PriFlashABegin		0
+#define SecFlashABegin		32
+#define SecFlashBBegin		36
+#define PriFlashAOff		0x0
+#define PriFlashBOff		0x100000
+#define SecFlashAOff		0x200000
+#define SecFlashBOff		0x280000
+#define INVALIDLOCNSTART	0x20270000
+#define INVALIDLOCNEND		0x20280000
+#define BlockEraseVal		0x30
+#define UNLOCKDATA1		0xaa
+#define UNLOCKDATA2		0x55
+#define UNLOCKDATA3		0xa0
+#define GETCODEDATA1		0xaa
+#define GETCODEDATA2		0x55
+#define GETCODEDATA3		0x90
+#define SecFlashASec1Off	0x200000
+#define SecFlashASec2Off	0x204000
+#define SecFlashASec3Off	0x206000
+#define SecFlashASec4Off	0x208000
+#define SecFlashAEndOff		0x210000
+#define SecFlashBSec1Off	0x280000
+#define SecFlashBSec2Off	0x284000
+#define SecFlashBSec3Off	0x286000
+#define SecFlashBSec4Off	0x288000
+#define SecFlashBEndOff		0x290000
+
+#define SECT32			32
+#define SECT33			33
+#define SECT34			34
+#define SECT35			35
+#define SECT36			36
+#define SECT37			37
+#define SECT38			38
+#define SECT39			39
+
+#define FLASH_SUCCESS	0
+#define FLASH_FAIL	-1
+
+#endif

board/ezkit533/flash.c

+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+	reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
+			     int bank_flag)
+{
+	int id = 0, i = 0;
+	static int FlagDev = 1;
+
+	id = get_codes();
+	if(FlagDev)	{
+#ifdef DEBUG
+		printf("Device ID of the Flash is %x\n", id);
+#endif
+		FlagDev = 0;
+	}
+	info->flash_id = id;
+
+	switch (bank_flag) {
+	case 0:
+		for (i = PriFlashABegin; i < SecFlashABegin; i++)
+			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+		info->size = 0x200000;
+		info->sector_count = 32;
+		break;
+	case 1:
+		info->start[0] = baseaddr + SecFlashASec1Off;
+		info->start[1] = baseaddr + SecFlashASec2Off;
+		info->start[2] = baseaddr + SecFlashASec3Off;
+		info->start[3] = baseaddr + SecFlashASec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	case 2:
+		info->start[0] = baseaddr + SecFlashBSec1Off;
+		info->start[1] = baseaddr + SecFlashBSec2Off;
+		info->start[2] = baseaddr + SecFlashBSec3Off;
+		info->start[3] = baseaddr + SecFlashBSec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	}
+	return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1, size_b2;
+	int i;
+
+	size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+	printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+	printf("Memory Map for the Flash\n");
+	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+	printf("Please type command flinfo for information on Sectors \n");
+#endif
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
+	size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
+	size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 >> 20);
+	}
+
+	(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+
+	return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id) {
+	case FLASH_PSD4256GV:
+		printf("ST Microelectronics ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int cnt = 0,i;
+	int prot,sect;
+
+	prot = 0;
+        for (sect = s_first; sect <= s_last; ++sect) {
+                if (info->protect[sect])
+                        prot++;
+        }
+
+	if (prot)
+                printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+        else
+                printf ("\n");	
+
+	cnt = s_last - s_first + 1;
+
+	if (cnt == FLASH_TOT_SECT) {
+		printf("Erasing flash, Please Wait \n");
+		if(erase_flash() < 0) {
+			printf("Erasing flash failed \n");
+			return FLASH_FAIL;
+		}
+	} else {
+		printf("Erasing Flash locations, Please Wait\n");
+		for (i = s_first; i <= s_last; i++) {
+			if (info->protect[i] == 0) {	/* not protected */
+				if(erase_block_flash(i, info->start[i]) < 0) {
+					printf("Error Sector erasing \n");
+					return FLASH_FAIL;
+				}
+			}
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int ret;
+
+	ret = write_data(addr, cnt, 1, (int *) src);
+	if(ret == FLASH_FAIL)
+		return ERR_NOT_ERASED;
+	return FLASH_SUCCESS;
+}
+
+
+int write_data(long lStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+	int d;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; (j < iNumWords);
+			j++, ulOffset += (lStride * 2)) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND)) {
+				printf("Invalid locations, Try writing to another location \n");
+				return FLASH_FAIL;
+			}
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset,&d);
+			if(d != 0xffff) {
+				printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+				return FLASH_FAIL;
+			}
+			unlock_flash(ulOffset);
+			if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+				printf("Error programming the flash \n");
+				return FLASH_FAIL;
+			}
+			iShift += 16;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset,&d);
+		if(d != 0xffff) {
+			printf("Flash already programmed. Please erase to reprogram \n");
+			printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		if(write_flash(ulOffset, pnData[i]) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+	long i = 0;
+	int j = 0;
+	long ulOffset = ulStart;
+	int iShift = 0;
+	int iNumWords = 2;
+	int nLeftover = lCount % 4;
+	int nHi, nLow;
+	int nSector = 0;
+
+	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+			if ((ulOffset >= INVALIDLOCNSTART)
+				&& (ulOffset < INVALIDLOCNEND))
+					return FLASH_FAIL;
+
+			get_sector_number(ulOffset, &nSector);
+			read_flash(ulOffset, &nLow);
+			ulOffset += (lStride * 2);
+			read_flash(ulOffset, &nHi);
+			ulOffset += (lStride * 2);
+			pnData[i] = (nHi << 16) | nLow;
+		}
+	}
+	if (nLeftover > 0) {
+		if ((ulOffset >= INVALIDLOCNSTART)
+			&& (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
+
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &pnData[i]);
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+	long addr;
+
+	addr = (CFG_FLASH_BASE + nOffset);
+	asm("ssync;");
+	*(unsigned volatile short *) addr = nValue;
+	asm("ssync;");
+	if(poll_toggle_bit(nOffset) < 0)
+		return FLASH_FAIL;
+	return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+	int nValue = 0x0;
+	long addr = (CFG_FLASH_BASE + nOffset);
+
+	if (nOffset != 0x2)
+		reset_flash();
+	asm("ssync;");
+	nValue = *(volatile unsigned short *) addr;
+	asm("ssync;");
+	*pnValue = nValue;
+	return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+	unsigned int u1,u2;
+	unsigned long timeout = 0xFFFFFFFF;
+	volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
+	while(1) {
+		if(timeout < 0)
+			break;
+		u1 = *(volatile unsigned short *)FB;
+		u2 = *(volatile unsigned short *)FB;
+		if((u1 & 0x0040) == (u2 & 0x0040))
+			return FLASH_SUCCESS;
+		if((u2 & 0x0020) == 0x0000)
+			continue;
+		u1 = *(volatile unsigned short *)FB;
+		if((u2 & 0x0040) == (u1 & 0x0040))
+			return FLASH_SUCCESS;
+		else {
+			reset_flash();
+			return FLASH_FAIL;
+		}
+		timeout--;
+	}
+	printf("Time out occured \n");
+	if(timeout <0)	return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+	write_flash(WRITESEQ1, RESET_VAL);
+	/* Wait for 10 micro seconds */
+	udelay(10);
+}
+
+int erase_flash(void)
+{
+	write_flash(WRITESEQ1, WRITEDATA1);
+	write_flash(WRITESEQ2, WRITEDATA2);
+	write_flash(WRITESEQ3, WRITEDATA3);
+	write_flash(WRITESEQ4, WRITEDATA4);
+	write_flash(WRITESEQ5, WRITEDATA5);
+	write_flash(WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(0x0000) < 0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashASec1Off) < 0)
+		return FLASH_FAIL;
+
+	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(PriFlashBOff) <0)
+		return FLASH_FAIL;
+
+	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+	if(poll_toggle_bit(SecFlashBOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+	long ulSectorOff = 0x0;
+
+	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+		return FALSE;
+
+	ulSectorOff = (address - CFG_FLASH_BASE);
+
+	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+	write_flash(ulSectorOff, BlockEraseVal);
+
+	if(poll_toggle_bit(ulSectorOff) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+	unsigned long ulOffsetAddr = ulOffset;
+	ulOffsetAddr &= 0xFFFF0000;
+
+	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+	int dev_id = 0;
+
+	write_flash(WRITESEQ1, GETCODEDATA1);
+	write_flash(WRITESEQ2, GETCODEDATA2);
+	write_flash(WRITESEQ3, GETCODEDATA3);
+
+	read_flash(0x0002, &dev_id);
+	dev_id &= 0x00FF;
+
+	reset_flash();
+
+	return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+
+	if (ulOffset >= SecFlashAOff) {
+		if ((ulOffset < SecFlashASec1Off)
+			&& (ulOffset < SecFlashASec2Off)) {
+				nSector = SECT32;
+		} else if ((ulOffset >= SecFlashASec2Off)
+			&& (ulOffset < SecFlashASec3Off)) {
+				nSector = SECT33;
+		} else if ((ulOffset >= SecFlashASec3Off)
+			&& (ulOffset < SecFlashASec4Off)) {
+				nSector = SECT34;
+		} else if ((ulOffset >= SecFlashASec4Off)
+			&& (ulOffset < SecFlashAEndOff)) {
+				nSector = SECT35;
+		}
+	} else if (ulOffset >= SecFlashBOff) {
+		if ((ulOffset < SecFlashBSec1Off)
+			&& (ulOffset < SecFlashBSec2Off)) {
+				nSector = SECT36;
+		}
+		if ((ulOffset < SecFlashBSec2Off)
+			&& (ulOffset < SecFlashBSec3Off)) {
+				nSector = SECT37;
+		}
+		if ((ulOffset < SecFlashBSec3Off)
+			&& (ulOffset < SecFlashBSec4Off)) {
+				nSector = SECT38;
+		}
+		if ((ulOffset < SecFlashBSec4Off)
+			&& (ulOffset < SecFlashBEndOff)) {
+				nSector = SECT39;
+		}
+	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+		nSector = ulOffset & 0xffff0000;
+		nSector = ulOffset >> 16;
+		nSector = nSector & 0x000ff;
+	}
+
+	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+		*pnSector = nSector;
+	}
+}

board/ezkit533/psd4256.h

+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTA_DIN	0x070000
+#define	PSD_PORTA_DOUT	0x070004
+#define	PSD_PORTA_DIR	0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CFG_FLASH1_BASE
+ * for Flash A and CFG_FLASH2_BASE for Flash B.
+ */
+
+#define	PSD_PORTB_DIN	0x070001
+#define	PSD_PORTB_DOUT	0x070005
+#define	PSD_PORTB_DIR	0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define	PSDA_PPICLK1	0x20		/* PPI Clock select bit 1		*/
+#define	PSDA_PPICLK0	0x10		/* PPI Clock select bit 0		*/
+#define	PSDA_VDEC_RST	0x08		/* Video decoder reset, 0 = RESET	*/
+#define	PSDA_VENC_RST	0x04		/* Video encoder reset, 0 = RESET	*/
+#define	PSDA_CODEC_RST	0x01		/* Codec reset, 0 = RESET		*/
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define	PSDA_LED9	0x20		/* LED 9, 1 = LED ON			*/
+#define	PSDA_LED8	0x10		/* LED 8, 1 = LED ON			*/
+#define	PSDA_LED7	0x08		/* LED 7, 1 = LED ON			*/
+#define	PSDA_LED6	0x04		/* LED 6, 1 = LED ON			*/
+#define	PSDA_LED5	0x02		/* LED 5, 1 = LED ON			*/
+#define	PSDA_LED4	0x01		/* LED 4, 1 = LED ON			*/
+

board/ezkit533/u-boot.lds

+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    board/ezkit533/ezkit533.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

board/stamp/Makefile

+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o stamp.o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/stamp/config.mk

+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x07FC0000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+

board/stamp/stamp.c

+/*
+ * U-boot - stamp.c STAMP board specific routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mem_init.h>
+#include "stamp.h"
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON  1 	
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)	
+#endif
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+	printf("Board: ADI BF533 Stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	printf("       Richard Klingler <richard@uclinux.net>\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	printf("SDRAM attributes:\n");
+	printf("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+		"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
+	(SDRAM_tRAS >> 6), ( SDRAM_tWR >> 19), (SDRAM_CL >> 2 ));
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", 128);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return (gd->bd->bi_memsize);
+}
+
+void swap_to(int device_id)
+{
+
+	if (device_id == ETHERNET)
+	{
+		*pFIO_DIR = PF0;
+		asm("ssync;");
+		*pFIO_FLAG_S = PF0;
+		asm("ssync;");
+	}
+	else if (device_id == FLASH)
+	{
+		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
+		*pFIO_FLAG_S = (PF4 | PF3 | PF2 );
+		*pFIO_MASKA_D = (PF8 | PF6 | PF5);
+		*pFIO_MASKB_D = (PF7);
+		*pFIO_POLAR = (PF8 | PF6 | PF5 );
+		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
+		*pFIO_FLAG_D = (PF4 | PF3 | PF2 );
+		asm("ssync;");
+	}
+	else {
+		printf("Unknown bank to switch\n");
+	}	
+	
+	return;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	int i;
+	int cf_stat = 0;
+
+	/* Check whether CF card is inserted */
+	*pFIO_EDGE = FIO_EDGE_CF_BITS;
+	*pFIO_POLAR = FIO_POLAR_CF_BITS;
+	for (i=0; i < 0x300 ; i++) asm("nop;");
+			
+	if ( (*pFIO_FLAG_S) & CF_STAT_BITS)
+	{
+		cf_stat = 0;
+	}
+	else
+	{
+		cf_stat = 1;
+	}
+
+	*pFIO_EDGE  = FIO_EDGE_BITS;
+	*pFIO_POLAR = FIO_POLAR_BITS;
+	
+
+	if (cf_stat)
+	{
+                printf ("Booting from COMPACT flash\n");
+
+		/* Set cycle time for CF */
+		*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+		for (i=0; i < 0x1000 ; i++) asm("nop;");
+
+		serial_setbrg();
+		ide_init();
+
+		setenv ("bootargs", "");
+		setenv ("bootcmd", "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000" );
+	}
+	else
+        {
+		printf ("Booting from FLASH\n");
+	}
+
+	return 1;
+}
+#endif
+
+#ifdef CONFIG_STAMP_CF
+
+void cf_outb(unsigned char val, volatile unsigned char* addr)
+{
+	/* 
+	 * Set PF1 PF0 respectively to 0 1 to divert address
+	 * to the expansion memory banks  
+	 */
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	*(addr) = val;
+	asm("ssync;");
+
+	/* Setback PF1 PF0 to 0 0 to address external 
+	 * memory banks  */
+	*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+	volatile unsigned char c;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	c = *(addr);
+	asm("ssync;");
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+
+	return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	for (i = 0;i < words; i++)
+	{
+		*(sect_buf + i) = *(addr);
+		asm("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	*pFIO_FLAG_S = CF_PF0;
+	*pFIO_FLAG_C = CF_PF1;
+	asm("ssync;");
+
+	for (i = 0;i < words; i++)
+	{
+		*(addr) = *(sect_buf + i);
+		asm("ssync;");
+	}
+
+	*pFIO_FLAG_C = CF_PF1_PF0;
+	asm("ssync;");
+}
+#endif
+
+void stamp_led_set(int LED1, int LED2, int LED3)
+{
+	*pFIO_INEN  &= ~( PF2 | PF3 | PF4);
+	*pFIO_DIR   |=  ( PF2 | PF3 | PF4);
+	
+	if(LED1 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF2;
+	else
+		*pFIO_FLAG_C = PF2;
+	if(LED2 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF3;
+	else
+		*pFIO_FLAG_C = PF3;
+	if(LED3 == STATUS_LED_OFF)
+		*pFIO_FLAG_S = PF4;
+	else
+		*pFIO_FLAG_C = PF4;
+	asm("ssync;");
+}
+
+void show_boot_progress(int status)
+{
+	switch(status){
+		case 1:	
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_ON);
+			break;
+		case 2:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_OFF);
+			break;
+		case 3:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_ON,STATUS_LED_ON);
+			break;	
+		case 4:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_OFF);			
+			break;
+		case 5:
+		case 6:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_OFF,STATUS_LED_ON);			
+			break;
+		case 7:
+		case 8:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_OFF);			
+			break;
+		case 9:
+		case 10:
+		case 11:
+		case 12:
+		case 13:
+		case 14:
+		case 15:
+			stamp_led_set(STATUS_LED_OFF,STATUS_LED_OFF,STATUS_LED_OFF);			
+			break;
+		default:
+			stamp_led_set(STATUS_LED_ON,STATUS_LED_ON,STATUS_LED_ON);			
+			break;
+	}
+}
+

board/stamp/stamp.h

+/*
+ * U-boot - stamp.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __STAMP_H__
+#define __STAMP_H__
+
+extern void init_Flags(void);
+
+extern volatile unsigned long *ambctl0;
+extern volatile unsigned long *ambctl1;
+extern volatile unsigned long *amgctl;
+
+extern unsigned long pll_div_fact;
+extern void serial_setbrg(void);
+extern void pll_set(int vco, int crystal_frq, int pll_div);
+
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 	0x0000
+#define FIO_POLAR_CF_BITS 	0x0000
+#define	FIO_EDGE_BITS  		0x1E0
+#define	FIO_POLAR_BITS  	0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 		0x00000060
+
+/* CF Flags used to switch between expansion and external
+ * memory banks
+ */
+#define CF_PF0			0x0001
+#define CF_PF1			0x0002
+#define CF_PF1_PF0		0x0003
+
+#endif

board/stamp/u-boot.lds

+/*
+ * U-boot - u-boot.lds
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf533/start.o		(.text)
+    cpu/bf533/start1.o		(.text)
+    cpu/bf533/traps.o		(.text)
+    cpu/bf533/interrupt.o	(.text)
+    cpu/bf533/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

cpu/bf533/Makefile

+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(CPU).a
+
+START	= start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
+OBJS	= cpu.o traps.o ints.o serial.o interrupts.o
+
+all:	.depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

cpu/bf533/bf533_serial.h

+/*
+ * U-boot - bf533_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on 
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001	Tony Z. Kou	tonyko@arcturusnetworks.com
+ * Copyright (C) 2001   Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf533_SERIAL_H
+#define _Bf533_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+extern int get_clock(void);
+int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
+
+struct {
+	unsigned char dl_high;
+	unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif

cpu/bf533/cache.S

+
+
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <asm/cpu/def_LPBlackfin.h>
+
+.text
+.align 2
+ENTRY(blackfin_icache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	IFLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	IFLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(blackfin_dcache_flush_range)
+	R2 = -32;
+        R2 = R0 & R2;
+        P0 = R2;
+        P1 = R1;
+        CSYNC;
+1:
+        FLUSH[P0++];
+        CC = P0 < P1(iu);
+        IF CC JUMP 1b(bp);
+        FLUSH[P0];
+        SSYNC;
+        RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(invalidate_entire_icache)
+        [--SP] = ( R7:5);
+                                                                                                                                                             
+        P0.L = (IMEM_CONTROL & 0xFFFF);
+        P0.H = (IMEM_CONTROL >> 16);
+        R7 = [P0];
+                                                                                                                                                             
+        /* Clear the IMC bit , All valid bits in the instruction
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,IMC_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before invalidating cache. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        /* Configures the instruction cache agian */
+        R6 = (IMC | ENICPLB);
+        R7 = R7 | R6;
+                                                                                                                                                             
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        ( R7:5) = [SP++];
+        RTS;
+
+/* Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+        [--SP] = ( R7:6);
+                                                                                                                                                             
+        P0.L = (DMEM_CONTROL & 0xFFFF);
+        P0.H = (DMEM_CONTROL >> 16);
+        R7 = [P0];
+                                                                                                                                                             
+        /* Clear the DMC[1:0] bits, All valid bits in the data
+         * cache are set to the invalid state
+         */
+        BITCLR(R7,DMC0_P);
+        BITCLR(R7,DMC1_P);
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        /* Configures the data cache again */
+                                                                                                                                                             
+        R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+        R7 = R7 | R6;
+                                                                                                                                                             
+        CLI R6;
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P0] = R7;
+        SSYNC;
+        STI R6;
+                                                                                                                                                             
+        ( R7:6) = [SP++];
+        RTS;
+
+ENTRY(blackfin_dcache_invalidate_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSHINV[P0++];
+	CC = P0 < P1 (iu);
+	IF CC JUMP 1b (bp);
+
+	/* If the data crosses a cache line, then we'll be pointing to
+	** the last cache line, but won't have flushed/invalidated it yet, so do
+	** one more.
+	*/
+	FLUSHINV[P0];
+	SSYNC;
+	RTS;

cpu/bf533/config.mk

+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-P5

cpu/bf533/cplbhdlr.S

+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. 
+ *
+ * Blackfin BF533/2.6 support : LG Soft India	
+ */
+
+
+/* Include an exception handler to invoke the CPLB manager
+ */
+
+#include <asm-blackfin/linkage.h>
+#include <asm/cplb.h>
+#include <asm/entry.h>
+
+
+.text
+ 
+.globl _cplb_hdr;
+.type _cplb_hdr, STT_FUNC;
+.extern _cplb_mgr;
+.type _cplb_mgr, STT_FUNC;
+.extern __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+.extern __cplb_miss_all_locked;
+.type __cplb_miss_all_locked, STT_FUNC;
+.extern __cplb_miss_without_replacement;
+.type __cplb_miss_without_replacement, STT_FUNC;
+.extern __cplb_protection_violation;
+.type __cplb_protection_violation, STT_FUNC;
+.extern panic_pv;
+
+.align 2;
+
+ENTRY(_cplb_hdr)
+	SSYNC;
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = ASTAT;
+	[--SP] = SEQSTAT;
+	[--SP] = I0;
+	[--SP] = I1;
+	[--SP] = I2;
+	[--SP] = I3;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC0;
+	[--SP] = LT1;
+	[--SP] = LB1;
+	[--SP] = LC1;
+	R2 = SEQSTAT;
+
+	/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
+	R2 <<= 26;
+	R2 >>= 26;
+
+	R1 = 0x23; /* Data access CPLB protection violation */
+	CC = R2 == R1;
+	IF !CC JUMP not_data_write;
+	R0 = 2;		/* is a write to data space*/
+	JUMP is_icplb_miss;
+
+not_data_write:
+	R1 = 0x2C; /* CPLB miss on an instruction fetch */
+	CC = R2 == R1;
+	R0 = 0;		/* is_data_miss == False*/
+	IF CC JUMP is_icplb_miss;
+
+	R1 = 0x26;
+	CC = R2 == R1;
+	IF !CC JUMP unknown;
+
+	R0 = 1;		/* is_data_miss == True*/
+
+is_icplb_miss:
+
+#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
+#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_ICACHE; 
+#endif
+#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_DCACHE; 
+#endif
+#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
+	R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; 
+#endif
+#else
+	R1 = 0;
+#endif
+
+	[--SP] = RETS;			
+	CALL _cplb_mgr;
+	RETS = [SP++];
+	CC = R0 == 0;
+	IF !CC JUMP not_replaced;
+	LC1 = [SP++];
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC0 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	I3 = [SP++];
+	I2 = [SP++];
+	I1 = [SP++];
+	I0 = [SP++];
+	SEQSTAT = [SP++];
+	ASTAT = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+unknown:
+	[--SP] = RETS;			
+	CALL __unknown_exception_occurred;
+	RETS = [SP++];
+	JUMP unknown;
+not_replaced:
+	CC = R0 == CPLB_NO_UNLOCKED;
+	IF !CC JUMP next_check;
+	[--SP] = RETS;			
+	CALL __cplb_miss_all_locked;
+	RETS = [SP++];
+next_check:
+	CC = R0 == CPLB_NO_ADDR_MATCH;
+	IF !CC JUMP next_check2;
+	[--SP] = RETS;			
+	CALL __cplb_miss_without_replacement;
+	RETS = [SP++];
+	JUMP not_replaced;
+next_check2:
+	CC = R0 == CPLB_PROT_VIOL;
+	IF !CC JUMP strange_return_from_cplb_mgr;
+	[--SP] = RETS;			
+	CALL __cplb_protection_violation;
+	RETS = [SP++];
+	JUMP not_replaced;
+strange_return_from_cplb_mgr:
+	IDLE;
+	CSYNC;
+	JUMP strange_return_from_cplb_mgr;
+
+/************************************
+ * Diagnostic exception handlers 
+ */	
+
+__cplb_miss_all_locked:
+	sp += -12;
+	R0 = CPLB_NO_UNLOCKED;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+ __cplb_miss_without_replacement:
+	sp += -12;
+	R0 = CPLB_NO_ADDR_MATCH;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+__cplb_protection_violation:
+	sp += -12;
+	R0 = CPLB_PROT_VIOL;
+	call panic_bfin;
+	SP += 12;
+	RTS;
+
+__unknown_exception_occurred:
+
+	/* This function is invoked by the default exception
+	 * handler, if it does not recognise the kind of
+	 * exception that has occurred. In other words, the
+	 * default handler only handles some of the system's
+	 * exception types, and it does not expect any others
+	 * to occur. If your application is going to be using
+	 * other kinds of exceptions, you must replace the
+	 * default handler with your own, that handles all the
+	 * exceptions you will use.
+	 * 
+	 * Since there's nothing we can do, we just loop here
+	 * at what we hope is a suitably informative label.
+	 */
+	
+	IDLE;
+do_not_know_what_to_do:
+	CSYNC;
+	JUMP __unknown_exception_occurred;
+
+	RTS;
+.__unknown_exception_occurred.end:
+.global __unknown_exception_occurred;
+.type __unknown_exception_occurred, STT_FUNC;
+
+panic_bfin:
+	RTS;
+

cpu/bf533/cplbmgr.S

+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Modification: Dec 07 2004
+ *	1. Correction in icheck_lock.  Valid lock entries were 
+ *	   geting victimized, for instruction cplb replacement.
+ *	2. Setup loop's are modified as now toolchain support's P Indexed
+ *	   addressing
+ *	   :LG Soft India
+ *
+ */
+
+/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
+ * is_data_miss==2 => Mark as Dirty, write to the clean data page
+ * is_data_miss==1 => Replace a data CPLB.
+ * is_data_miss==0 => Replace an instruction CPLB.
+ *
+ * Returns:
+ * CPLB_RELOADED	=> Successfully updated CPLB table.
+ * CPLB_NO_UNLOCKED	=> All CPLBs are locked, so cannot be evicted.This indicates 
+ *				that the CPLBs in the configuration tablei are badly 
+ *				configured, as this should never occur.
+ * CPLB_NO_ADDR_MATCH	=> The address being accessed, that triggered the exception, 
+ *				is not covered by any of the CPLBs in the configuration 
+ *				table. The application isi presumably misbehaving.
+ * CPLB_PROT_VIOL	=> The address being accessed, that triggered thei exception, 
+ *				was not a first-write to a clean Write Back Data page, 
+ *				and so presumably is a genuine violation of the page's 
+ *				protection attributes. The application is misbehaving.
+ */
+#define ASSEMBLY
+
+#include <asm-blackfin/linkage.h>
+#include <asm-blackfin/blackfin.h>
+#include <asm-blackfin/cplbtab.h>
+#include <asm-blackfin/cplb.h>
+ 	
+.text
+ 
+.align 2;
+ENTRY(_cplb_mgr)
+
+	[--SP]=( R7:0,P5:0 );
+
+	CC = R0 == 2;
+	IF CC JUMP dcplb_write;
+
+	CC = R0 == 0;
+	IF !CC JUMP dcplb_miss_compare;
+
+	/* ICPLB Miss Exception. We need to choose one of the
+	* currently-installed CPLBs, and replace it with one
+	* from the configuration table.	
+ 	*/
+
+	P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
+	P4.H = (ICPLB_FAULT_ADDR >> 16);
+
+	P1 = 16;
+	P5.L = page_size_table;
+	P5.H = page_size_table;
+
+	P0.L = (ICPLB_DATA0 & 0xFFFF);
+	P0.H = (ICPLB_DATA0 >> 16);
+	R4 = [P4];		/* Get faulting address*/
+	R6 = 64;		/* Advance past the fault address, which*/
+	R6 = R6 + R4;		/* we'll use if we find a match*/
+	R3 = ((16 << 8) | 2);	/* Extract mask, bits 16 and 17.*/
+
+	R5 = 0;
+isearch:
+
+	R1 = [P0-0x100];	/* Address for this CPLB */
+	
+	R0 = [P0++];		/* Info for this CPLB*/
+	CC = BITTST(R0,0);	/* Is the CPLB valid?*/
+	IF !CC JUMP nomatch;	/* Skip it, if not.*/
+	CC = R4 < R1(IU);	/* If fault address less than page start*/
+	IF CC JUMP nomatch;	/* then skip this one.*/
+	R2 = EXTRACT(R0,R3.L) (Z);	/* Get page size*/
+	P1 = R2;
+	P1 = P5 + (P1<<2);	/* index into page-size table*/
+	R2 = [P1];		/* Get the page size*/
+	R1 = R1 + R2;		/* and add to page start, to get page end*/
+	CC = R4 < R1(IU);	/* and see whether fault addr is in page.*/
+	IF !CC R4 = R6;		/* If so, advance the address and finish loop.*/
+	IF !CC JUMP isearch_done;
+nomatch:
+	/* Go around again*/
+	R5 += 1;
+	CC = BITTST(R5, 4);	/* i.e CC = R5 >= 16*/
+	IF !CC JUMP isearch;
+
+isearch_done:
+	I0 = R4;		/* Fault address we'll search for*/
+	
+	/* set up pointers */
+	P0.L = (ICPLB_DATA0 & 0xFFFF);
+	P0.H = (ICPLB_DATA0 >> 16);
+
+	/* The replacement procedure for ICPLBs */
+
+	P4.L = (IMEM_CONTROL & 0xFFFF);
+	P4.H = (IMEM_CONTROL >> 16);
+
+	/* disable cplbs */
+	R5 = [P4];		/* Control Register*/
+	BITCLR(R5,ENICPLB_P);
+	CLI R1;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R1;
+
+	R1 = -1;		/* end point comparison */
+	R3 = 16;		/* counter */
+
+	/* Search through CPLBs for first non-locked entry */
+	/* Overwrite it by moving everyone else up by 1 */
+icheck_lock:
+	R0 = [P0++];
+	R3 = R3 + R1;
+	CC = R3 == R1;
+	IF CC JUMP all_locked;
+	CC = BITTST(R0, 0);		/* an invalid entry is good */
+	IF !CC JUMP ifound_victim;
+	CC = BITTST(R0,1);		/* but a locked entry isn't */
+	IF CC JUMP icheck_lock;
+
+ifound_victim:
+#ifdef CONFIG_CPLB_INFO
+	R7 = [P0 - 0x104];
+	P2.L = ipdt_table;
+	P2.H = ipdt_table;
+	P3.L = ipdt_swapcount_table;
+	P3.H = ipdt_swapcount_table;
+	P3 += -4;
+icount:
+	R2 = [P2];	/* address from config table */			
+	P2 += 8;
+	P3 += 8;
+	CC = R2==-1;
+	IF CC JUMP icount_done;
+	CC = R7==R2;
+	IF !CC JUMP icount;
+	R7 = [P3];
+	R7 += 1;
+	[P3] = R7;
+	CSYNC;
+icount_done:
+#endif
+	LC0=R3;
+	LSETUP(is_move,ie_move) LC0;
+is_move: 
+	R0 = [P0];
+	[P0 - 4] = R0;
+	R0 = [P0 - 0x100];
+	[P0-0x104] = R0; 
+ie_move:P0+=4;
+	
+	/* We've made space in the ICPLB table, so that ICPLB15
+	 * is now free to be overwritten. Next, we have to determine
+	 * which CPLB we need to install, from the configuration
+	 * table. This is a matter of getting the start-of-page
+	 * addresses and page-lengths from the config table, and
+	 * determining whether the fault address falls within that
+	 * range.
+ 	 */
+	
+	P2.L = ipdt_table;
+	P2.H = ipdt_table;
+#ifdef	CONFIG_CPLB_INFO
+	P3.L = ipdt_swapcount_table;
+	P3.H = ipdt_swapcount_table;
+	P3 += -8;
+#endif
+	P0.L = page_size_table;
+	P0.H = page_size_table;
+
+	/* Retrieve our fault address (which may have been advanced
+	 * because the faulting instruction crossed a page boundary).
+	 */
+
+	R0 = I0;
+
+	/* An extraction pattern, to get the page-size bits from
+	 * the CPLB data entry. Bits 16-17, so two bits at posn 16.
+	 */
+
+	R1 = ((16<<8)|2);
+inext:	R4 = [P2++];	/* address from config table */			
+	R2 = [P2++];	/* data from config table */
+#ifdef	CONFIG_CPLB_INFO
+	P3 += 8;
+#endif
+
+	CC = R4 == -1;	/* End of config table*/
+	IF CC JUMP no_page_in_table;
+
+	/* See if failed address > start address */
+	CC = R4 <= R0(IU);
+ 	IF !CC JUMP inext;
+
+	/* extract page size (17:16)*/
+	R3 = EXTRACT(R2, R1.L) (Z);
+
+	/* add page size to addr to get range */
+
+	P5 = R3;
+	P5 = P0 + (P5 << 2);	/* scaled, for int access*/
+	R3 = [P5];
+	R3 = R3 + R4;
+
+	/* See if failed address < (start address + page size) */
+	CC = R0 < R3(IU);
+	IF !CC JUMP inext;
+
+	/* We've found a CPLB in the config table that covers
+	 * the faulting address, so install this CPLB into the
+	 * last entry of the table.
+	 */
+
+	P1.L = (ICPLB_DATA15 & 0xFFFF);		/*ICPLB_DATA15*/
+	P1.H = (ICPLB_DATA15 >> 16);
+	[P1] = R2;
+	[P1-0x100] = R4;
+#ifdef	CONFIG_CPLB_INFO
+	R3 = [P3];
+	R3 += 1;
+	[P3] = R3;
+#endif
+
+	/* P4 points to IMEM_CONTROL, and R5 contains its old
+	 * value, after we disabled ICPLBS. Re-enable them.
+	 */
+
+	BITSET(R5,ENICPLB_P);
+	CLI R2;
+	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R2;
+
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+/* FAILED CASES*/
+no_page_in_table:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_NO_ADDR_MATCH;
+        RTS;
+all_locked:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_NO_UNLOCKED;
+        RTS;
+prot_violation:
+        ( R7:0,P5:0 ) = [SP++];
+        R0 = CPLB_PROT_VIOL;
+        RTS;
+
+dcplb_write:
+
+	/* if a DCPLB is marked as write-back (CPLB_WT==0), and
+	 * it is clean (CPLB_DIRTY==0), then a write to the
+	 * CPLB's page triggers a protection violation. We have to
+	 * mark the CPLB as dirty, to indicate that there are
+	 * pending writes associated with the CPLB.
+	 */
+
+	P4.L = (DCPLB_STATUS & 0xFFFF);
+	P4.H = (DCPLB_STATUS >> 16);
+	P3.L = (DCPLB_DATA0 & 0xFFFF);
+	P3.H = (DCPLB_DATA0 >> 16);
+	R5 = [P4];	
+
+	/* A protection violation can be caused by more than just writes
+	 * to a clean WB page, so we have to ensure that:
+	 * - It's a write
+	 * - to a clean WB page
+	 * - and is allowed in the mode the access occurred.
+	 */
+
+	CC = BITTST(R5, 16);	/* ensure it was a write*/
+	IF !CC JUMP prot_violation;
+
+	/* to check the rest, we have to retrieve the DCPLB.*/
+
+	/* The low half of DCPLB_STATUS is a bit mask*/
+
+	R2 = R5.L (Z);	/* indicating which CPLB triggered the event.*/
+	R3 = 30;	/* so we can use this to determine the offset*/
+	R2.L = SIGNBITS R2;
+	R2 = R2.L (Z);	/* into the DCPLB table.*/
+	R3 = R3 - R2;
+	P4 = R3;
+	P3 = P3 + (P4<<2);
+	R3 = [P3];	/* Retrieve the CPLB*/
+
+	/* Now we can check whether it's a clean WB page*/
+
+	CC = BITTST(R3, 14);	/* 0==WB, 1==WT*/
+	IF CC JUMP prot_violation;
+	CC = BITTST(R3, 7);	/* 0 == clean, 1 == dirty*/
+	IF CC JUMP prot_violation;
+
+	/* Check whether the write is allowed in the mode that was active.*/
+
+	R2 = 1<<3;		/* checking write in user mode*/
+	CC = BITTST(R5, 17);	/* 0==was user, 1==was super*/
+	R5 = CC;
+	R2 <<= R5;		/* if was super, check write in super mode*/
+	R2 = R3 & R2;
+	CC = R2 == 0;
+	IF CC JUMP prot_violation;	
+
+	/* It's a genuine write-to-clean-page.*/
+
+	BITSET(R3, 7);		/* mark as dirty*/
+	[P3] = R3;		/* and write back.*/
+	CSYNC;
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+dcplb_miss_compare:
+
+	/* Data CPLB Miss event. We need to choose a CPLB to
+	 * evict, and then locate a new CPLB to install from the
+	 * config table, that covers the faulting address.
+	 */
+
+	P1.L = (DCPLB_DATA15 & 0xFFFF);	
+	P1.H = (DCPLB_DATA15 >> 16);
+
+	P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
+	P4.H = (DCPLB_FAULT_ADDR >> 16);
+	R4 = [P4];
+	I0 = R4;
+
+	/* The replacement procedure for DCPLBs*/
+
+	R6 = R1;	/* Save for later*/
+
+	/* Turn off CPLBs while we work.*/
+	P4.L = (DMEM_CONTROL & 0xFFFF);
+	P4.H = (DMEM_CONTROL >> 16);
+	R5 = [P4];
+	BITCLR(R5,ENDCPLB_P);
+	CLI R0;
+	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R0;
+
+	/* Start looking for a CPLB to evict. Our order of preference
+	 * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
+	 * are no good.
+	 */
+
+	I1.L = (DCPLB_DATA0 & 0xFFFF);
+	I1.H = (DCPLB_DATA0 >> 16);
+	P1 = 3;
+	P2 = 16;
+	I2.L = dcplb_preference;
+	I2.H = dcplb_preference;
+	LSETUP(sdsearch1, edsearch1) LC0 = P1;
+sdsearch1:
+	R0 = [I2++];		/* Get the bits we're interested in*/
+	P0 = I1;		/* Go back to start of table*/
+	LSETUP (sdsearch2, edsearch2) LC1 = P2;
+sdsearch2:
+	R1 = [P0++];		/* Fetch each installed CPLB in turn*/
+	R2 = R1 & R0;		/* and test for interesting bits.*/
+	CC = R2 == 0;		/* If none are set, it'll do.*/
+	IF !CC JUMP skip_stack_check;
+
+	R2 = [P0 - 0x104]; 	/* R2 - PageStart */
+	P3.L = page_size_table; /* retrive end address */
+	P3.H = page_size_table; /* retrive end address */
+	R3 = 0x2;		/* 0th - position, 2 bits -length */
+	nop;			/*Anamoly 05000209*/
+	R7 = EXTRACT(R1,R3.l);
+	R7 = R7 << 2;		/* Page size index offset */
+	P5 = R7;
+	P3 = P3 + P5;
+	R7 = [P3];		/* page size in 1K bytes */
+
+	R7 = R7 << 0xA;		/* in bytes * 1024*/
+	R7 = R2 + R7;		/* R7 - PageEnd */
+	R4 = SP; 		/* Test SP is in range */
+
+	CC = R7 < R4;		/* if PageEnd < SP */
+	IF CC JUMP dfound_victim;
+	R3 = 0x284;		/* stack length from start of trap till the point */
+				/* 20 stack locations for future modifications */
+	R4 = R4 + R3;	
+	CC = R4 < R2;		/* if SP + stacklen < PageStart */
+	IF CC JUMP dfound_victim;
+skip_stack_check:
+
+edsearch2: NOP;
+edsearch1: NOP;
+
+	/* If we got here, we didn't find a DCPLB we considered
+	 * replacable, which means all of them were locked.
+	 */
+	
+	JUMP all_locked;
+dfound_victim:
+
+#ifdef CONFIG_CPLB_INFO
+	R1 = [P0 - 0x104];
+	P2.L = dpdt_table;
+	P2.H = dpdt_table;
+	P3.L = dpdt_swapcount_table;
+	P3.H = dpdt_swapcount_table;
+	P3 += -4;
+dicount:
+	R2 = [P2];
+	P2 += 8;
+	P3 += 8;
+	CC = R2==-1;
+	IF CC JUMP dicount_done;
+	CC = R1==R2;
+	IF !CC JUMP dicount;
+	R1 = [P3];
+	R1 += 1;
+	[P3] = R1;
+	CSYNC;
+dicount_done:
+#endif
+
+	/* Clean down the hardware loops*/
+	R2 = 0;
+	LC1 = R2;
+	LC0 = R2;
+
+	/* There's a suitable victim in [P0-4] (because we've
+	 * advanced already). If it's a valid dirty write-back
+	 * CPLB, we need to flush the pending writes first.
+	 */
+
+	CC = BITTST(R1, 0);	/* Is it valid?*/
+	IF !CC JUMP Ddoverwrite;/* nope.*/
+	CC = BITTST(R1, 7);	/* Is it dirty?*/
+	IF !CC JUMP Ddoverwrite (BP);	/* Nope.*/
+	CC = BITTST(R1, 14);	/* Is it Write-Through?*/
+	IF CC JUMP Ddoverwrite;	/* Yep*/
+
+	/* This is a dirty page, so we need to flush all writes
+	 * that are pending on the page.
+	 */
+
+	/* Retrieve the page start address*/
+        R0 = [P0 - 0x104];
+	[--sp] = rets;
+	CALL dcplb_flush;	/* R0==CPLB addr, R1==CPLB data*/
+	rets = [sp++];
+Ddoverwrite:
+
+	/* [P0-4] is a suitable victim CPLB, so we want to
+	 * overwrite it by moving all the following CPLBs
+	 * one space closer to the start.
+	 */
+	
+	R1.L = ((DCPLB_DATA15+4) & 0xFFFF);		/*DCPLB_DATA15+4*/
+	R1.H = ((DCPLB_DATA15+4) >> 16);
+	R0 = P0;
+
+	/* If the victim happens to be in DCPLB15,
+	 * we don't need to move anything.
+	 */
+
+	CC = R1 == R0;
+	IF CC JUMP de_moved;
+	R1 = R1 - R0;
+	R1 >>= 2;
+	P1 = R1;
+	LSETUP(ds_move, de_move) LC0=P1;
+ds_move:
+	 R0 = [P0++];	/* move data */
+	[P0 - 8] = R0;
+	R0 = [P0-0x104]	/* move address */
+de_move: [P0-0x108] = R0;
+
+	/* We've now made space in DCPLB15 for the new CPLB to be
+	 * installed. The next stage is to locate a CPLB in the
+	 * config table that covers the faulting address.
+	 */
+
+de_moved:NOP;
+	R0 = I0;		/* Our faulting address */
+
+	P2.L = dpdt_table;
+	P2.H = dpdt_table;
+#ifdef	CONFIG_CPLB_INFO
+	P3.L = dpdt_swapcount_table;
+	P3.H = dpdt_swapcount_table;
+	P3 += -8;
+#endif
+
+	P1.L = page_size_table;
+	P1.H = page_size_table;
+
+	/* An extraction pattern, to retrieve bits 17:16.*/
+
+	R1 = (16<<8)|2;
+dnext:	R4 = [P2++];	/* address */			
+	R2 = [P2++];	/* data */
+#ifdef	CONFIG_CPLB_INFO
+	P3 += 8;
+#endif
+
+	CC = R4 == -1;
+	IF CC JUMP no_page_in_table;
+
+	/* See if failed address > start address */
+	CC = R4 <= R0(IU);
+ 	IF !CC JUMP dnext;
+
+	/* extract page size (17:16)*/
+	R3 = EXTRACT(R2, R1.L) (Z);
+
+	/* add page size to addr to get range */
+
+	P5 = R3;
+	P5 = P1 + (P5 << 2);
+	R3 = [P5];
+	R3 = R3 + R4;
+
+	/* See if failed address < (start address + page size) */
+	CC = R0 < R3(IU);
+	IF !CC JUMP dnext;
+
+	/* We've found the CPLB that should be installed, so
+	 * write it into CPLB15, masking off any caching bits
+	 * if necessary.
+	 */
+
+	P1.L = (DCPLB_DATA15 & 0xFFFF);
+	P1.H = (DCPLB_DATA15 >> 16);
+
+	/* If the DCPLB has cache bits set, but caching hasn't
+	 * been enabled, then we want to mask off the cache-in-L1
+	 * bit before installing. Moreover, if caching is off, we
+	 * also want to ensure that the DCPLB has WT mode set, rather
+	 * than WB, since WB pages still trigger first-write exceptions
+	 * even when not caching is off, and the page isn't marked as
+	 * cachable. Finally, we could mark the page as clean, not dirty,
+	 * but we choose to leave that decision to the user; if the user
+	 * chooses to have a CPLB pre-defined as dirty, then they always
+	 * pay the cost of flushing during eviction, but don't pay the
+	 * cost of first-write exceptions to mark the page as dirty.
+	 */
+
+#ifdef CONFIG_BLKFIN_WT
+	BITSET(R6, 14);		/* Set WT*/
+#endif
+
+	[P1] = R2;
+	[P1-0x100] = R4;
+#ifdef	CONFIG_CPLB_INFO
+	R3 = [P3];
+	R3 += 1;
+	[P3] = R3;
+#endif
+
+	/* We've installed the CPLB, so re-enable CPLBs. P4
+	 * points to DMEM_CONTROL, and R5 is the value we
+	 * last wrote to it, when we were disabling CPLBs.
+	 */
+
+	BITSET(R5,ENDCPLB_P);
+	CLI R2;
+	.align 8;
+	[P4] = R5;
+	SSYNC;
+	STI R2;
+
+	( R7:0,P5:0 ) = [SP++];
+	R0 = CPLB_RELOADED;
+	RTS;
+
+.data
+.align 4;
+page_size_table:
+.byte4	0x00000400;	/* 1K */
+.byte4	0x00001000;	/* 4K */
+.byte4	0x00100000;	/* 1M */
+.byte4	0x00400000;	/* 4M */
+
+.align 4;
+dcplb_preference:
+.byte4	0x00000001;	/* valid bit */
+.byte4	0x00000082;	/* dirty+lock bits */
+.byte4	0x00000002;	/* lock bit */

cpu/bf533/cpu.c

+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+
+#define SSYNC() asm("ssync;")
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#define ANOMALY_05000158		0x200	
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+static unsigned int icplb_table[16][2]={
+			{0xFFA00000, L1_IMEMORY},
+			{0x00000000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
+			{0x00400000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
+			{0x07C00000, SDRAM_IKERNEL},    /*SDRAM_Page14*/
+			{0x00800000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
+			{0x00C00000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
+			{0x01000000, SDRAM_IGENERIC},	/*SDRAM_Page4*/
+			{0x01400000, SDRAM_IGENERIC},	/*SDRAM_Page5*/
+			{0x01800000, SDRAM_IGENERIC},	/*SDRAM_Page6*/
+			{0x01C00000, SDRAM_IGENERIC},	/*SDRAM_Page7*/
+			{0x02000000, SDRAM_IGENERIC},	/*SDRAM_Page8*/
+			{0x02400000, SDRAM_IGENERIC},	/*SDRAM_Page9*/
+			{0x02800000, SDRAM_IGENERIC},	/*SDRAM_Page10*/
+			{0x02C00000, SDRAM_IGENERIC},	/*SDRAM_Page11*/
+			{0x03000000, SDRAM_IGENERIC},	/*SDRAM_Page12*/
+			{0x03400000, SDRAM_IGENERIC},	/*SDRAM_Page13*/
+};
+
+static unsigned int dcplb_table[16][2]={
+			{0xFFA00000,L1_DMEMORY},	
+			{0x00000000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
+			{0x00400000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
+			{0x07C00000,SDRAM_DKERNEL},	/*SDRAM_Page15*/
+			{0x00800000,SDRAM_DGENERIC},	/*SDRAM_Page2*/
+			{0x00C00000,SDRAM_DGENERIC},	/*SDRAM_Page3*/
+			{0x01000000,SDRAM_DGENERIC},	/*SDRAM_Page4*/
+			{0x01400000,SDRAM_DGENERIC},	/*SDRAM_Page5*/
+			{0x01800000,SDRAM_DGENERIC},	/*SDRAM_Page6*/
+			{0x01C00000,SDRAM_DGENERIC},	/*SDRAM_Page7*/
+			{0x02000000,SDRAM_DGENERIC},	/*SDRAM_Page8*/
+			{0x02400000,SDRAM_DGENERIC},	/*SDRAM_Page9*/
+			{0x02800000,SDRAM_DGENERIC},	/*SDRAM_Page10*/
+			{0x02C00000,SDRAM_DGENERIC},	/*SDRAM_Page11*/
+			{0x03000000,SDRAM_DGENERIC},	/*SDRAM_Page12*/
+			{0x20000000,SDRAM_EBIU},	/*For Network */	
+};
+
+
+			
+			
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	__asm__ __volatile__
+	("cli r3;"
+	"P0 = %0;"
+	"JUMP (P0);"
+	:
+	: "r" (L1_ISRAM)
+	);
+
+	return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	return 0;
+}
+
+void icache_enable(void)
+{
+	unsigned int *I0,*I1;
+	int i;
+
+	I0 = (unsigned int *)ICPLB_ADDR0;
+	I1 = (unsigned int *)ICPLB_DATA0;
+	
+	for(i=0;i<16;i++){
+		*I0++ = icplb_table[i][0];
+		*I1++ = icplb_table[i][1];
+		}
+	cli();
+	SSYNC();
+	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+	SSYNC();
+	sti();
+}
+
+void icache_disable(void)
+{
+	cli();
+	SSYNC();
+	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+	SSYNC();
+	sti();
+}
+
+int icache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)IMEM_CONTROL;
+
+	if( value & (IMC|ENICPLB) )
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+	unsigned int *I0,*I1;
+	unsigned int temp;
+	int i;
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	for(i=0;i<16;i++){
+		*I0++ = dcplb_table[i][0];
+		*I1++ = dcplb_table[i][1];
+		}
+	cli();
+	temp = *(unsigned int *)DMEM_CONTROL; 
+	SSYNC();
+	*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
+	SSYNC();
+	sti();
+}
+		
+
+void dcache_disable(void)
+{
+	cli();
+	SSYNC();
+	*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
+	SSYNC();
+	sti();
+}
+
+int dcache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)DMEM_CONTROL;
+	if( value & (ENDCPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}