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Commit a61da72b authored by Dirk Behme's avatar Dirk Behme Committed by Andy Fleming
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fsl_esdhc: Touch only relevant sys ctrl bits


Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).

Do this by read/modify/write instead of just a 32bit write.

Signed-off-by: default avatarDirk Behme <dirk.behme@de.bosch.com>
Acked-by: default avatarStefano Babic <sbabic@denx.de>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent ca6d4d0f
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......@@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc)
int timeout = 1000;
/* Reset the entire host controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
/* Wait until the controller is available */
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
......@@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc)
esdhc_write32(&regs->scr, 0x00000040);
#endif
esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
......@@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs)
unsigned long timeout = 100; /* wait max 100 ms */
/* reset the controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
/* hardware clears the bit when it is done */
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
......
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