We put the bootpg for the secondary cpus into memory and use
BPTR to get to it.  This is a step towards converting to the
ePAPR boot methodology.  Also, the code is written to
deal properly with more than 4GB of RAM.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

There are several items in the config file that were hardcoded
but that should really be based on other config options, since
the regions are contiguous and depend on being so.  This cleans
that up a bit.  Also, add BR_PHYS_ADDR() macro to convert
addresses into the proper format for BR registers.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

It's currently a long and should be phys_size_t.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location.  Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region.  Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.

Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

You can't actually have both, and with some coming changes to
change the memory map for the board and support 36-bit physical,
we need the extra BAT that is being consumed by having both.

I also make non-PCI configs build cleanly, for the sake of sanity.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

We don't actually ever do this, remove the code so we
can stop maintaining it.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>

This removes in nand.h code that is verbatim duplicated from bbm.h,
including directly bbm.h in nand.h. The previous state of affairs
prevented compiling code for a board hosting both NAND and OneNAND chips.

Reported-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Scott Wood <scottwood@freescale.com>

Reported-by: Alessandro Rubini <rubini-list@gnudd.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.

Singed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

CONFIG_ENV_ADDR should be (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE).

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

This patch fixes a problem on systems where the NOR flash is attached
to a 64 bit bus.  The toggle bit detection in flash_toggle() is based
on the assumption that the same flash address is read twice without
any other interjacent flash accesses.  However, on 32 bit systems the
function flash_read64() [as currently implemented] does not perform
an atomic 64 bit read - instead, this is broken down into two 32 bit
read accesses on addresses "addr" and "addr + 4".  So instead of
reading a 64 bit value twice from "addr", we see a sequence of 4 32
bit reads from "addr", "addr + 4", "addr", and "addr + 4".  The
consequence is that flash_toggle() fails to work.

This patch implements a simple, but somewhat ugly solution, as it
avoids the use of flash_read64() in this critical place (by breaking
it down manually into 32 bit read operations) instead of rewriting
flash_read64() such to perform atomic 64 bit reads as one could
expect.  However, such a rewrite would require the use of floating
point load operations, which becomes pretty complex:

	save MSR;
	set Floating Point Enable bit in MSR;
	use "lfd" instruction to perform atomic 64 bit read;
	use "stfd" to store value to temporary variable on stack;
	load u64 value from temporary variable;
	restore saved MSR;
	return u64 value;

The benefit-cost ratio of such an implementation was considered too
bad to actually attempt this, especially as we can expect that such
an implementation would not only have a bigger memory footprint but
also cause a performance degradation.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Stefan Roese <sr@denx.de>

This patch brings PMC440 board support up to date:

- fix GPIO configuration
- add misc_init_f()
- use better values for usbact variable
- fix USB 2.0 phy reset sequence
- shrink BAR2 to save PCI address space
- add FDT support

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

This patch fixes the PMC440 BSP commands painit and selfreset

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

This patch fixes esd's loadpci command when not all
memory on adapter boards is accessable via PCI.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

-Codingstyle cleanup
-Remove unused GPIO define

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Xilinx ppc440 and ppc405 have many similarities. This patch merge the
config files of both infrastuctures

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>

Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
pin multiplexing correctly

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>

There's currently an off-by-one bug in fdt_subnode_offset_namelen()
which causes it to keep searching after it's finished the subnodes of
the given parent, and into the subnodes of siblings of the original
node which come after it in the tree.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

fdt_add_mem_rsv() requires space for a struct fdt_reserve_entry
(16 bytes), so make sure that fdt_resize at least adds that much
padding, no matter what the location or size of the fdt is.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Andy Fleming <afleming@freescale.com>

The patch is following the commit 39243840

mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache

This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>

also, the r2 is used as global data pointer.

Signed-off-by: Dave Liu <daveliu@freescale.com>

The current calculation will fail to cover all memory if
its size is not a power of two.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>