Patch (SHA1: bd694244)
dfu: Introduction of the "dfu_hash_algo" env variable for checksum method
setting

already introduced more generic handling of the crc32 calculation.
Up till now the CRC32 of received data was calculated unconditionally.
This patch changes this and from now - by default the crc32 is NOT
calculated anymore.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Sometimes, a zero-length packet is required at the end of an IN
transaction so that the host knows the device is done sending data.
Enhance ci_udc to send a zlp when necessary. See the comments for
more details.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

usb_gadget_unregister_driver() is called to tear down the USB device mode
stack. Fix the driver to stop the USB HW (which causes any attached host
to notice the disappearance of the device), and free all allocations
(which obviously prevents memory leaks).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

If allocation of the ep0 req fails, clean up all the allocations that
were made in ci_udc_probe().

Signed-off-by: Stephen Warren <swarren@nvidia.com>

ci_ep_alloc_request() avoids allocating multiple request objects for ep0
by keeping a record of the first req allocated for ep0, and always
returning that instead of allocating a new req. However, if this req is
ever freed, the record of the previous allocation is not cleared, so
ci_ep_alloc_request() will keep returning this stale pointer. Fix
ci_ep_free_request() to clear the record of the previous allocation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect().
Remove the duplication by simply calling udc_disconnect() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Signed-off-by: Tom Rini <trini@ti.com>

'r' of rESR_RTLF is a mistake of E.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

This fixes checkpatch's warning.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

This family is supported by the TPS65218 PMIC.  Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).

Signed-off-by: Tom Rini <trini@ti.com>

Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.

Signed-off-by: Tom Rini <trini@ti.com>

Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher.  Add a similar hook to start with.

Signed-off-by: Tom Rini <trini@ti.com>

Signed-off-by: Tom Rini <trini@ti.com>

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

in almost all cases we need the i2c commands within the u-boot shell.
So we enable them within the common section.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>

After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.

Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

commit a0a37183 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"

cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

Enable support of nand ecclayout command.

Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.

Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared.  When SPL booting, this is handled by setting gd
to point to SRAM in s_init.  However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.

Signed-off-by: Tom Rini <trini@ti.com>

We have two contexts for booting these platforms.  One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads.  The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.

In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus).  In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.

Signed-off-by: Tom Rini <trini@ti.com>

The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>

The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices.  As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.

Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

updates documentation with explanation on how to select ECC schemes.

Signed-off-by: Pekon Gupta <pekon@ti.com>

This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta <pekon@ti.com>

GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel

Signed-off-by: Pekon Gupta <pekon@ti.com>

OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.

Signed-off-by: Pekon Gupta <pekon@ti.com>

GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL:    SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
        which is called before probing for devices, hence any ONFI parameter
        information is not available during GPMC initialization.

Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.

This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.

Signed-off-by: Pekon Gupta <pekon@ti.com>

As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

So porting following commit from linux kernel
    commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
    Author: David Mosberger <davidm@egauge.net>  (preserving authorship)
    mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

Signed-off-by: Pekon Gupta <pekon@ti.com>

As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>

Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author:     Brian Norris <computersforpeace@gmail.com>
mtd: nand: don't use read_buf for 8-bit ONFI transfers

  Use a repeated read_byte() instead of read_buf(), since for x16 buswidth
  devices, we need to avoid the upper I/O[16:9] bits. See the following
  commit for reference:

  commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
  Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
  Date:   Thu Dec 5 22:22:04 2013 +0100

      mtd: nand: don't use {read,write}_buf for 8-bit transfers

  Now, I think that all barriers to probing ONFI on x16 devices are
  removed, so remove the check from nand_flash_detect_onfi().

Signed-off-by: Pekon Gupta <pekon@ti.com>