Patch by Jon Loeliger, 01. May 2006

Signed-off-by: dzu@denx.de <dzu@denx.de>

Signed-off-by: dzu@denx.de <dzu@eddie.localdomain>

Signed-off-by: dzu@denx.de <dzu@denx.de>

is configured; othrwise DMA accesses aren't cache coherent which
causes for example USB to fail.

  - Fix dbau1x00 boards broken by dbau1550 patch
    PLL:s were not set for boards other than 1550.
    Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
    Default boot is now bootp for cards other than 1550.
  Patch by Thomas Lange Aug 10 2005

   - fix some compiler/parser error, if using m68k tool chain
   - optical fix for protect on/off all messages, if using more
     then one bank
  Patch by Jens Scharsig, 28 July 2005

Some more NAND cleanup and small fixes.

Necessary defines and data structures were copied to DoC specific files
so that legacy NAND code could be entirely removed from u-boot tree
in the near future.

Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]

  Patch by Stefano Babic, 29 Mar 2006

* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000

Merge with /home/mk/8-benq/u-boot

  - Add Intel legacy lock/unlock support to common CFI driver

    On some Intel flash's (e.g. Intel J3) legacy unlocking is
    supported, meaning that unlocking of one sector will unlock
    all sectors of this bank. Using this feature, unlocking
    of all sectors upon startup (via env var "unlock=yes") will
    get much faster.

  - Fixed problem with multiple reads of envronment variable
    "unlock" as pointed out by Reinhard Arlt & Anders Larsen.

  - Removed unwanted linefeeds from "protect" command when
    CFG_FLASH_PROTECTION is enabled.

  - Changed p3p400 board to use CFG_FLASH_PROTECTION

  Patch by Stefan Roese, 01 Apr 2006

* Changes/fixes for drivers/cfi_flash.c:
  - Correctly handle the cases where CFG_HZ != 1000 (several
    XScale-based boards)
  - Fix the timeout calculation of buffered writes (off by a
    factor of 1000)
  Patch by Anders Larsen, 31 Mar 2006

405 SDRAM: - The SDRAM parameters can now be defined in the board
             config file and the 405 SDRAM controller values will
             be calculated upon bootup (see PPChameleonEVB).
             When those settings are not defined in the board
             config file, the register setup will be as it is now,
             so this implementation should not break any current
             design using this code.

             Thanks to Andrea Marson from DAVE for this patch.

440 DDR:   - Added function sdram_tr1_set to auto calculate the
             TR1 value for the DDR.
           - Added ECC support (see p3p440).

Patch by Stefan Roese, 17 Mar 2006

Patch by Stefano Babic, 29 Mar 2006

CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core
frequency.

make the pxa i2c driver work with the monahans cpu.